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M16C/5L Group, M16C/56 Group
FASTMODE (SCL mode select bit) (b5)
When using the fast-mode I
mode) and set fVIIC to 4 MHz or more.
Rewrite the FASTMODE bit when the ES0 bit in the S1D0 register is 0 (disabled).
ACKBIT (ACK bit) (b6)
The ACK bit is enabled in master reception, slave reception, or slave address reception. When
receiving a slave address, the SDAMM pin level during the ACK clock pulse is determined by a
combination of bits ALS and ACKBIT in the S1D0 register and the received slave address.
When receiving data, the SDAMM pin level during the ACK clock pulse is determined by the ACKBIT
bit. Table 22.5 lists the SDAMM Pin Level during the ACK Clock Pulse.
Table 22.5
SDAMM Pin Level during the ACK Clock Pulse
Received
ALS Bit in the
Content
S1D0 Register
Slave
Address
Data
ACKCLK (ACK clock bit) (b7)
When the ACKCLK bit is 1 (ACK clock present), an ACK clock is generated immediately after 1-byte
data is transmitted or received (8 clocks).
When the ACKCLK bit is 0 (no ACK clock), no ACK clock is generated after 1-byte data is transmitted
or received (8 clocks). At the falling edge of data transmission/reception (the falling edge of the eighth
clock), the IR bit in the IICIC register becomes 1 (interrupt requested).
Do not write to this bit when transmitting/receiving data.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
2
C-bus standard (maximum 400 kbps), set the FASTMODE bit to 1 (fast-
ACKBIT Bit in the
S20 Register
0
0
1
0
1
1
0
—
1
Slave Address Content
When the MSLAD bit in the
S4D0 register is 0:
Matched with bits SAD6 to
SAD0 in the S0D0 register.
When the MSLAD bit is 1:
Matched with bits SAD6 to
SAD0 in any of registers
S0D0 to S0D2.
0000000b
Others
—
—
—
—
—
2
22. Multi-master I
C-bus Interface
SDAMM Pin Level at
ACK Clock
Low (ACK)
Low (ACK)
High (NACK)
High (NACK)
Low (ACK)
High (NACK)
Low (ACK)
High (NACK)
Page 508 of 803
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