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M16C/5L Group, M16C/56 Group
21.3
Operations
21.3.1
Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transmit/receive clock to transmit/receive data. Table
21.5 lists the Clock Synchronous Serial I/O Mode Specifications.
Table 21.5
Clock Synchronous Serial I/O Mode Specifications
Item
Data format
Transmit/receive clock
Transmit/receive control
Transmission start
conditions
Reception start
conditions
Interrupt request
generation timing
Error detection
Selectable functions
i = 0 to 4
Notes:
1.
These requirements do not have to be set in any particular order. If transmission/reception is started while an
external clock is selected and the TXEPT bit in the UiC0 register is 1 (no data present in transmit register), meet
the last requirement at either of the following timings:
• The CKPOL bit in the UiC0 register is 0 (transmit data is output at the falling edge of transmit/receive clock
and receive data is input at the rising edge) and the external clock is high.
• The CKPOL bit is 1 (transmit data is output at the rising edge of transmit/receive clock and receive data is
input at the falling edge) and the external clock is low.
2.
If an overrun error occurs, the receive data of the UiRB register will be undefined. The IR bit in the SiRIC register
remains unchanged.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Character length: 8 bits
• CKDIR bit in the UiMR register = 0 (internal clock):
fj = f1SIO, f2SIO, f8SIO, f32SIO
n = setting value of UiBRG register (00h to FFh)
• CKDIR bit = 1 (external clock): input from CLKi pin
Selectable from CTS , RTS , or CTS / RTS function disabled (UART0 to UART3)
To start transmission, satisfy the following requirements
• The TE bit in the UiC1 register is 1 (transmission enabled)
• The TI bit in the UiC1 register is 0 (data presents in UiTB register)
• When CTS function is selected, input on the CTSi pin is low
To start reception, satisfy the following requirements
• The RE bit in the UiC1 register is 1 (reception enabled)
• The TE bit in the UiC1 register is 1 (transmission enabled)
• The TI bit in the UiC1 register is 0 (data presents in the UiTB register)
For transmission, one of the following conditions can be selected
• The UiIRS bit in the UiC1 register is 0 (transmit buffer empty):
When transferring data from the UiTB register to the UARTi transmit register (at start of
transmission)
• The UiIRS bit is 1 (transfer completed):
When the serial interface completes sending data from the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
(2)
Overrun error
This error occurs if the serial interface starts receiving the next unit of data before reading
the UiRB register and receiving the seventh bit of the next unit of data
• CLK polarity selection
Data input/output can be selected to occur synchronously with the rising or falling edge of
the transmit/receive clock
• LSB first, MSB first selection
Whether to start transmitting/receiving the data from bit 0 or from bit 7 can be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic
This function inverts the logic value of the transmit/receive data
21. Serial Interface UARTi (i = 0 to 4)
Specification
fj
-------------------- -
(
)
2 n
+
1
(1)
(1)
Page 450 of 803
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