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M16C/5L Group, M16C/56 Group
28.17.3.5 Restart Condition in Slave Mode
When a restart condition is detected in slave mode, the successive processes may not be executed
correctly. In slave mode, do not use a restart condition.
28.17.3.6 Requirements to Start Transmission/Reception in Slave Mode
When transmission/reception is started in slave mode and the TXEPT bit in the UiC0 register is 1 (no
data present in transmit register), meet the last requirement when the external clock is high.
Requirements to start transmission (in no particular order):
•
The TE bit in the U2C1 register is 1 (transmission enabled).
•
The TI bit in the U2C1 register is 0 (data present in the UiTB register).
Requirements to start reception (in no particular order):
•
The RE bit in the U2C1 register is 1 (reception enabled).
•
The TE bit in the U2C1 register is 1 (transmission enabled).
•
The TI bit in the U2C1 register is 0 (data present in the UiTB register).
28.17.4 Special Mode 4 (SIM Mode)
(Technical update number: TN-M16C-101-0309)
After reset is deasserted, a transmit interrupt request is generated by setting bits U2IRS and U2ERE in
the U2C1 register to 1 (transmission completed, error signal output), then setting the TE bit to 1
(transmission enabled) and the transmission data to the U2TB register. Therefore, when using SIM
mode, make sure to set the IR bit to 0 (interrupt not requested) after setting these bits.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
28. Usage Notes
Page 792 of 803
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