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M16C/5L Group, M16C/56 Group
21.3.3.3
Arbitration
The MCU determines whether the transmit data matches data input to the SDA2 pin on the rising edge
of SCL2. If it does not match the input data, arbitration takes place at the SDA2 pin by stopping data
output.
The ABC bit in the U2SMR register determines the update timing for the ABT bit in the U2RB register.
When the ABC bit is 0 (update per bit), the ABT bit becomes 1 as soon as a data discrepancy is
detected. If not detected, the ABT bit becomes 0. When the ABC bit is 1 (update per byte), the ABT bit
becomes 1 on the falling edge of the eighth bit of SCL2 if any discrepancy is detected. In this ABC bit
setting, the ABT bit should be set to 0 after ACK detection of 1-byte is completed to start the next 1-byte
transmission/reception.
When the ALS bit in the U2SMR2 register is set to 1 (SDA output stop enabled), an arbitration lost
occurs. As soon as the ABT bit becomes 1, the SDA2 pin becomes high-impedance.
21.3.3.4
SCL Control and Clock Synchronization
Data transmission/reception in I
"Transfer to U2RB Register and Interrupt Timing". The clock speed increase makes it difficult to secure
the required time for ACK generation and data transmit procedure. The I
wait-state insertion to secure this required time and a function of clock synchronization with a wait-state
inserted by other devices.
The SWC bit in the U2SMR2 register is used to insert a wait-state for ACK generation. When the SWC
bit is set to 1 (the SCL2 pin is held low after the eighth bit of SCL2 is received), the SCL2 pin is held low
on the falling edge of the eighth bit of SCL2. When the SWC bit is set to 0 (no wait-state/wait-state
cleared), the SCL2 line is released.
When the SWC2 bit in the U2SMR2 register is set to 1 (the SCL2 pin is held low), the SCL2 pin is
forced low even during transmission or reception. When the SWC2 bit is set to 0 (transmit/receive clock
is output at the SCL2 pin), the SCL2 line is released to output the transmit/receive clock.
The SWC9 bit in the U2SMR4 register is used to insert a wait-state for checking received acknowledge
bits. While the CKPH bit in the U2SMR3 register is 1 (clock delayed), when the SWC9 bit is set to 1 (the
SCL2 pin is held low after the ninth bit of the SCL2 is received), the SCL2 pin is held low on the falling
edge of the ninth bit of SCL2. When the SWC9 bit is set to 0 (no wait-state/wait-state cleared), the
SCL2 line is released.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
2
C mode uses the transmit/receive clock as shown in Figure 21.15
21. Serial Interface UARTi (i = 0 to 4)
2
C mode supports a function of
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