Renesas M16C/50 Series User Manual page 810

M16C/5L Group, M16C/56 Group
INT Interrupt
28.8.7
•
Either a low level of at least tw(INL) width or a high level of at least tw(INH) width is necessary for
the signal input to pins INT0 through INT5 , regardless of the CPU operation clock.
•
If the POL bit in registers INT0IC to INT5IC or bits IFSR7 to IFSR0 in the IFSR register are
changed, the IR bit may inadvertently become 1 (interrupt requested). Be sure to set the IR bit to 0
(interrupt not requested) after changing any of these register bits.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
28. Usage Notes
Page 773 of 803