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M16C/5L Group, M16C/56 Group
Table 15.17
Registers and Settings in Programmable Output Mode
Register
PCLKR
CPSRF
TCKDIVC0
PWMFS
TACS0 to TACS2
TAPOFS
TAOW
TAi1
TABSR
ONSF
TRGSR
UDF
TAi
TAiMR
i = 1, 2, and 4
Notes:
1.
This table does not describe a procedure.
2.
This applies when the POFSi bit in the TAPOFS register is 0.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Bit
PCLK0
Select the count source.
CPSR
Write 1 to reset the clock prescaler.
TCDIV00
Select a clock used prior to dividing timer AB frequency.
PWMFSi
Set to 1.
7 to 0
Select the count source.
POFSi
Select the output polarity.
Set to 0 to disable output waveform change, and set to 1 to
TAiOW
enable output waveform change.
15 to 0
Set a low-level pulse width.
Set to 1 when starting counting.
TAiS
Set to 0 when stopping counting.
TAiOS
Set to 0.
TAZIE
Set to 0.
TA0TGH to TA0TGL Select a count trigger.
TAiTGH to TAiTGL
Select a count trigger.
TAiUD
Set to 0.
TAiP
Set to 0.
15 to 0
Set a high-level pulse width.
7 to 0
Refer to the TAiMR register below.
(1)
Function and Setting
(2)
(2)
15. Timer A
Page 271 of 803
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