Renesas M16C/50 Series User Manual page 550

M16C/5L Group, M16C/56 Group
ICK1 and ICK0 (I
Rewrite these bits when the ES0 bit in the S1D0 register is 0 (I
by setting all the bits ICK1 to ICK0, bits ICK4 to ICK2 in the S4D0 register, and the PCLK0 bit in the
PCLKR register. Refer to 22.3.1.2 "Bit Rate and Duty Cycle".
2
Table 22.7 I C-bus System Clock Select Bits
S4D0 Register
ICK4 Bit ICK3 Bit
0
0
0
0
0
0
1
–: 0 or 1
Only set the values listed above.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
2
C-bus system clock select bit) (b7-b6)
ICK2 Bit
0 0
0 0
0 0
0 1
1 0
1 1
0 0
22. Multi-master I
2
C interface disabled). fVIIC is selected
S3D0 Register
ICK1 Bit ICK0 Bit
0 0
0 1
1 0
– –
– –
– –
– –
2
C-bus Interface
fVIIC
fIIC divided-by-2
fIIC divided-by-4
fIIC divided-by-8
fIIC divided-by-2.5
fIIC divided-by-3
fIIC divided-by-5
fIIC divided-by-6
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