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M16C/5L Group, M16C/56 Group
21.2.6
UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 to 4)
UARTi Transmit/Receive Control Register 0 (i = 0 to 4)
b7 b6 b5 b4
b3
b2
b1
CLK1 to CLK0 (UiBRG count source select bit) (b1-b0)
When bits CLK1 to CLK0 are 00b (f1SIO or f2SIO selected), select f1SIO or f2SIO by the PCLK1 bit in
the PCLKR register.
Set bits CLK1 to CLK0 after setting registers UCLKSEL0 and PCLKR.
If bits CLK1 to CLK0 are changed, set the UiBRG register.
CRD (CTS/RTS disable bit) (b4)
When the CRD bit is 1 ( CTS / RTS function disabled), the CTSi / RTSi pin can be used as an I/O port.
Set the CRD bit in the U4C0 register to 1 ( CTS / RTS function disabled).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
b0
U0C0, U1C0, U2C0
U4C0, U3C0
Bit Symbol
Bit Name
CLK0
UiBRG count source select
bit
CLK1
CRS
CTS/RTS function select bit
TXEPT
Transmit register empty flag
CRD
CTS/RTS disable bit
NCH
Data output select bit
CKPOL
CLK polarity select bit
UFORM
Bit order select bit
21. Serial Interface UARTi (i = 0 to 4)
Address
024Ch, 025Ch, 026Ch
029Ch, 02ACh
Function
b1
b0
0
0 : f1SIO or f2SIO selected
0
1 : f8SIO selected
1
0 : f32SIO selected
1
1 : Do not set
Enabled when CRD is 0
0 : CTS function selected
1 : RTS function selected
0 : Data present in transmit register
(transmission in progress)
1 : No data present in transmit register
(transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : Pins TXDi/SDAi and SCLi are CMOS
output
1 : Pins TXDi/SDAi and SCLi are N-channel
open drain output
0 : Transmit data is output at the falling
edge of transmit/receive clock and
receive data is input at the rising edge
1 : Transmit data is output at the rising
edge of transmit/receive clock and
receive data is input at the falling edge
0 : LSB first
1 : MSB first
Reset Value
0000 1000b
0000 1000b
RW
RW
RW
RW
RO
RW
RW
RW
RW
Page 439 of 803
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