Page 1 REJ09B0185-0230Z M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES Before using this material, please visit our website to verify that this is the most updated document available. Rev. 2.30 Revision date: Sep 01, 2004...
Page 2 Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers con- tact Renesas Technology Corp.
Page 3: How To Use This Manual
How to Use This Manual 1. Introduction This hardware manual provides detailed information on the M16C/62P Group (M16C/62P, M16C/62PT) of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below.
Page 4: Overview
• Sample programs • Introduction to the basic functions in the M16C family • Programming method with Assembly and C languages RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc. NOTES : 1. Before using this material, please visit the our website to confirm that this is the most current document...
Page 5: Table Of Contents
Table of Contents 1. Overview ___________________________________________________ 1 1.1 Applications ......................... 1 1.2 Performance Outline....................2 1.3 Block Diagram ......................5 1.4 Product List ........................7 1.5 Pin Configuration ....................... 13 1.6 Pin Description......................17 2. Central Processing Unit (CPU) ________________________________ 22 2.1 Data Registers (R0, R1, R2 and R3)................
Page 7 10.5 System Clock Protection Function ................ 85 10.6 Oscillation Stop and Re-oscillation Detect Function ........... 85 10.6.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) ........... 86 10.6.2 Operation When CM27 bit = 0 (Oscillation Stop and Re-oscillation Detect Interrupt) .... 86 10.6.3 How to Use Oscillation Stop and Re-oscillation Detect Function ..........
Page 8 14.1.3 Effect of Software Wait ....................... 115 _______ 14.1.4 Effect of RDY Signal ........................115 14.2 DMA Transfer Cycles ..................... 117 14.3 DMA Enable ......................118 14.4 DMA Request ......................118 14.5 Channel Priority and DMA Transfer Timing ............119 15.
Page 9 22.5.1 User ROM and Boot ROM Areas ....................273 22.5.2 ROM Code Protect Function ...................... 273 23. Electrical Characteristics __________________________________ 274 23.1 Electrical Characteristics (M16C/62P)..............274 23.2 Electrical Characteristics (M16C/62PT) ............... 313 24. Usage Precaution _________________________________________ 326 24.1 Reset ........................326 24.2 Bus ..........................
Page 11 Appendix 1. Package Dimensions ______________________________ 359 Appendix 2. Differences Between M16C/62P and M16C/62A _________ 361 Register Index............364...
Page 12 SFR Page Reference Register Symbol Page Register Symbol Page Address Address 0000h 0040h 0001h 0041h 0002h 0042h 0003h 0043h Processor mode register 0 INT3 interrupt control register INT3IC 0004h 0044h Timer B5 interrupt control register TB5IC Processor mode register 1 0005h 0045h System clock control register 0...
Page 13 SFR Page Reference Register Symbol Page Register Symbol Page Address Address 0080h Timer B3, 4, 5 count start flag TBSR 0340h 0081h 0341h 0082h 0342h Timer A1-1 register TA11 0083h 0343h 0084h 0344h Timer A2-1 register TA21 0085h 0345h 0086h 0346h Timer A4-1 register TA41...
Page 14 SFR Page Reference Register Symbol Page Register Symbol Page Address Address 124, 139 Count start flag TABSR 0380h 03C0h A/D register 0 03C1h 125, 139 Clock prescaler reset flag CPSRF 0381h 03C2h A/D register 1 One-shot start flag ONSF 0382h 03C3h 125, 150 Trigger select register...
Page 16: Performance Outline
1. Overview M16C/62P Group (M16C/62P, M16C/62PT) 1.2 Performance Outline Table 1.1 to table 1.3 list performance outline of M16C/62P group (M16C/62P, M16C/62PT). Table 1.1 Performance Outline of M16C/62P group (M16C/62P) (128-pin version) Item Performance M16C/62P Number of Basic Instructions 91 instructions Minimum Instruction Execution Time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V)
Page 17 1. Overview M16C/62P Group (M16C/62P, M16C/62PT) Table 1.2 Performance outline of M16C/62P group (M16C/62P, M16C/62PT) (100-pin version) Item Performance (Note 4) M16C/62P M16C/62PT Number of Basic Instructions 91 instructions Minimum Instruction Execution Time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Page 18 1. Overview M16C/62P Group (M16C/62P, M16C/62PT) Table 1.3 Performance outline of M16C/62P group (M16C/62P, M16C/62PT) (80-pin version) Item Performance M16C/62P M16C/62PT Number of Basic Instructions 91 instructions Minimum Instruction Execution Time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Page 19: Block Diagram
M16C/62P Group (M16C/62P, M16C/62PT) 1.3 Block Diagram Figure 1.1 is a block diagram of the M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin ver- sion, figure 1.2 is a block diagram of the M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version. Port P0...
Page 20 4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program. Figure 1.2 M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram page 6...
Page 21: Product List
Tables 1.4 to 1.7 list the product list, figure 1.3 shows the type numbers, memory sizes and packages, table 1.8 lists the product code of flash memory version and ROMless version for M16C/62P, and table 1.9 lists the product code of flash memory version for M16C/62PT. Figure 1.4 shows the marking diagram of flash memory version and ROMless version for M16C/62P, and figure 1.5 shows the marking diagram of flash...
Page 22 1. Overview M16C/62P Group (M16C/62P, M16C/62PT) Table 1.5 Product List (2) (M16C/62P) As of Sep. 2004 Type No. ROM Capacity Remarks ROM Capacity Package Type 100P6S-A M30622MHP-XXXFP M30622MHP-XXXGP 16 Kbytes 100P6Q-A M30623MHP-XXXGP 128P6Q-A M30624MHP-XXXFP 100P6S-A 24 Kbytes 100P6Q-A M30624MHP-XXXGP 384 Kbytes...
Page 23 1. Overview M16C/62P Group (M16C/62P, M16C/62PT) Table 1.6 Product List (3) (T version (M16C/62PT)) As of Sep. 2004 Type No. ROM Capacity RAM Capacity Package Type Remarks M3062CM6T-XXXFP 100P6S-A M3062CM6T-XXXGP 100P6Q-A 48 Kbytes 4 Kbytes M3062EM6T-XXXGP 80P6S-A M3062CM8T-XXXFP 100P6S-A 64 Kbytes...
Page 24 1. Overview M16C/62P Group (M16C/62P, M16C/62PT) Type No. M 3 0 6 2 6 M H P – X X X F P Package type: FP : Package 100P6S-A GP : Package 80P6Q-A, 100P6Q-A, 128P6Q-A ROM No. Omitted for flash memory version and...
Page 25 The product without marking of chip version of the flash memory version and the ROMless version corresponds to the chip version “A”. Figure 1.4 Marking Diagram of Flash Memory version and ROMless version for M16C/62P (Top View) page 11...
Page 26 1. Overview M16C/62P Group (M16C/62P, M16C/62PT) Table 1.9 Product Code of Flash Memory version for M16C/62PT Internal ROM Internal ROM (User ROM Area (Block A, Block 1) Operating Product Without Block 1) Package Ambient Code Program Temperature Temperature Program Temperature...
Page 27: Pin Configuration
1. Overview M16C/62P Group (M16C/62P, M16C/62PT) 1.5 Pin Configuration Figures 1.6 to 1.9 show the pin configurations (top view). PIN CONFIGURATION (top view) P1_0/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P5_0/WRL/WR P0_4/AN0_4/D4 P5_1/WRH/BHE P0_3/AN0_3/D3 P5_2/RD P0_2/AN0_2/D2 P5_3/BCLK P0_1/AN0_1/D1 P0_0/AN0_0/D0 P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT...
Page 28 1. Overview M16C/62P Group (M16C/62P, M16C/62PT) PIN CONFIGURATION (top view) P4_4/CS0 P0_7/AN0_7/D7 <VCC2> P0_6/AN0_6/D6 P4_5/CS1 P4_6/CS2 P0_5/AN0_5/D5 P4_7/CS3 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P5_0/WRL/WR P0_2/AN0_2/D2 P5_1/WRH/BHE P0_1/AN0_1/D1 P5_2/RD P0_0/AN0_0/D0 P5_3/BCLK M16C/62P Group P10_7/AN7/KI3 P5_4/HLDA P10_6/AN6/KI2 P5_5/HOLD (M16C/62P, M16C/62PT) P10_5/AN5/KI1 P5_6/ALE P10_4/AN4/KI0 P5_7/RDY/CLKOUT P10_3/AN3...
Page 29 1. Overview M16C/62P Group (M16C/62P, M16C/62PT) PIN CONFIGURATION (top view) P1_2/D10 P4_2/A18 P1_1/D9 P4_3/A19 <VCC2> P1_0/D8 P4_4/CS0 P0_7/AN0_7/D7 P4_5/CS1 P0_6/AN0_6/D6 P4_6/CS2 P0_5/AN0_5/D5 P4_7/CS3 P0_4/AN0_4/D4 P5_0/WRL/WR P0_3/AN0_3/D3 P5_1/WRH/BHE P0_2/AN0_2/D2 P5_2/RD P0_1/AN0_1/D1 P5_3/BCLK P0_0/AN0_0/D0 M16C/62P Group P5_4/HLDA P10_7/AN7/KI3 P5_5/HOLD P10_6/AN6/KI2 (M16C/62P, M16C/62PT)
Page 30 1. Overview M16C/62P Group (M16C/62P, M16C/62PT) PIN CONFIGURATION (top view) P0_6/AN0_6 P4_3 P0_5/AN0_5 P5_0 P0_4/AN0_4 P5_1 P0_3/AN0_3 P5_2 P0_2/AN0_2 P5_3 P0_1/AN0_1 P5_4 P0_0/AN0_0 P5_5 P10_7/AN7/KI3 P5_6 P10_6/AN6/KI2 P5_7/CLKOUT P10_5/AN5/KI1 M16C/62P Group P6_0/CTS0/RTS0 P10_4/AN4/KI0 P6_1/CLK0 (M16C/62P, M16C/62PT) P10_3/AN3 P6_2/RXD0/SCL0 P10_2/AN2 P6_3/TXD0/SDA0...
Page 31 M16C/62P Group (M16C/62P, M16C/62PT)
Page 32: Pin Description
1. Overview M16C/62P Group (M16C/62P, M16C/62PT) Table 1.11 Pin Description (100-pin and 128-pin Version) (2) Power Signal Name Pin Name I/O Type Description Supply Main clock input VCC1 I/O pins for the main clock generation circuit. Connect a ceramic resonator or...
Page 33 M16C/62P Group (M16C/62P, M16C/62PT)
Page 34 1. Overview M16C/62P Group (M16C/62P, M16C/62PT) Table 1.13 Pin Description (80-pin Version) (1) Power Signal Name Pin Name I/O Type Description Supply Power supply input VCC1, Apply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin.
Page 35 M16C/62P Group (M16C/62P, M16C/62PT)
Page 36: Central Processing Unit (Cpu)
2. Central Processing Unit (CPU) M16C/62P Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.
Page 37: Frame Base Register (Fb)
2. Central Processing Unit (CPU) M16C/62P Group (M16C/62P, M16C/62PT) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
Page 38: Memory
M16C/62P Group (M16C/62P, M16C/62PT) 3. Memory Figure 3.1 is a memory map of the M16C/62P group. The address space extends the 1M bytes from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte internal ROM is allocated to the addresses from F0000h to FFFFFh.
Page 39: Special Function Register (Sfr)
M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) 4. Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functions. Table 4.1 to 4.6 list the SFR information. Table 4.1 SFR information (1) Address Register Symbol...
Page 40 4. Special Function Register (SFR) M16C/62P Group (M16C/62P, M16C/62PT) Table 4.2 SFR information (2) R e g i s t e r S y m b o l A f t e r R e s e t A d d r e s s...
Page 41 M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) Table 4.3 SFR information (3) Register Symbol After Reset Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h Flash Identification Register FIDR XXXXXX00b 01B5h Flash Memory Control Register 1...
Page 42 4. Special Function Register (SFR) M16C/62P Group (M16C/62P, M16C/62PT) Table 4.4 SFR information (4) Register Symbol After Reset Address 0340h Timer B3, 4, 5 Count Start Flag TBSR 000XXXXXb 0341h Timer A1-1 Register TA11 0342h 0343h Timer A2-1 Register TA21...
Page 43 M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) Table 4.5 SFR information (5) Register Symbol After Reset Address Count Start Flag TABSR 0380h 0381h Clock Prescaler Reset Fag CPSRF 0XXXXXXXb 0382h One-Shot Start Flag ONSF Trigger Select Register TRGSR...
Page 44 • “00000010b” where the PM01 to PM00 bits in the PM0 register are “01b” (memory expansion mode) or “11b” (microprocessor mode) 3. These registers do not exist in M16C/62P (80-pin version), and M16C/62PT (80-pin version). X : Nothing is mapped to this bit...
Page 45: Reset
5. Reset M16C/62P Group (M16C/62P, M16C/62PT) 5. Reset Hardware reset 1, voltage down detection reset (hardware reset 2), software reset, watchdog timer reset and oscillation stop detection reset are available to reset the microcomputer. 5.1 Hardware Reset 1 ____________ The microcomputer resets pins, the CPU and SFR by setting the RESET pin. If the supply voltage meets the recommended operating conditions, the microcomputer resets all pins when an “L”...
Page 46: Software Reset
5. Reset M16C/62P Group (M16C/62P, M16C/62PT) Recommended operation voltage VCC1 VCC1 RESET RESET 0.2VCC1 0.2VCC1 or below or below Supply a clock with td(P-R) + 2 0 or more cycles to the XIN pin NOTES: 1. If VCC1>VCC2, the VCC2 voltage must be lower than that of VCC1 when the power is being turned on or off.
Page 47 5. Reset M16C/62P Group (M16C/62P, M16C/62PT) VCC1, VCC2 More than d(P-R) 20 cycles are needed Microprocessor mode BYTE = H RESET BCLK 28cycles BCLK Content of reset vector FFFFDh Address FFFFCh FFFFEh Microprocessor Content of reset vector mode BYTE = L...
Page 48 5. Reset M16C/62P Group (M16C/62P, M16C/62PT) ____________ Table 5.1 Pin Status When RESET Pin Level is “L” Status Pin Name CNVSS = VCC1 CNVSS = VSS BYTE = VSS BYTE = VCC Input port Data input Data input Input port...
Page 49 6. Voltage Detection Circuit Note 6. Voltage Detection Circuit is described in the M16C/62P only as an example. The M16C/62PT do not use this function. The voltage detection circuit monitors the voltage applied to the VCC1 pin in Vdet3 and Vdet 4. The VC26 to VC27 bits in the VCR2 register determine whether this circuit is enabled or disabled.
Page 50 6. Voltage Detection Circuit M16C/62P Group (M16C/62P, M16C/62PT) ( 1 ) V o l t a g e D o w n D e t e c t i o n I n t e r r u p t R e g i s t e r...
Page 51 6. Voltage Detection Circuit M16C/62P Group (M16C/62P, M16C/62PT) 5.0V 5.0V Vdet4 Vdet3r VCC1 Vdet3 Vdet3s RESET Internal Reset Signal VC13 bit in Indefinite VCR1 register Set to “1” by program (reset level detect circuit enable) VC26 bit in Indefinite VCR2 register Set to “1”...
Page 52 6. Voltage Detection Circuit M16C/62P Group (M16C/62P, M16C/62PT) 6.1 Voltage Down Detection Interrupt If the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled), the voltage down detection interrupt request is generated when the voltage applied to the VCC1 pin is above or below Vdet4.
Page 53 6. Voltage Detection Circuit M16C/62P Group (M16C/62P, M16C/62PT) Voltage down detection interrupt generation circuit DF1, DF0 The D42 bit is set to “0” (not detected) by program. the VC27 bit is set to “0” Voltage Down Detection Circuit (voltage down detect circuit disabled), the D42 bit is set to “0”.
Page 54 6. Voltage Detection Circuit M16C/62P Group (M16C/62P, M16C/62PT) 6.2 Limitations on Exiting Stop Mode The voltage down detection interrupt is immediately generated and the microcomputer exits stop mode if the CM10 bit in the CM1 register is set to “1” under the conditions below.
Page 55 M16C/62P Group (M16C/62P, M16C/62PT) 7. Processor Mode Note 7. Processor Mode is described in the M16C/62P (128-pin version and 100-pin version) only as an example. The M16C/62P (80-pin version) and M16C/62PT do not use memory expansion mode, and microprocessor mode.
Page 56 7. Processor Mode M16C/62P Group (M16C/62P, M16C/62PT) 7.2 Setting Processor Modes Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register. Table 7.2 shows the processor mode after hardware reset. Table 7.3 shows the PM01 to PM00 bit set values and processor modes.
Page 57 7. Processor Mode M16C/62P Group (M16C/62P, M16C/62PT) Processor Mode Register 0 Symbol Address After Reset 0004h 00000000b (CNVSS pin = L) 00000011b (CNVSS pin = H) Bit symbol Bit Name Function b1 b0 Processor Mode Bit PM00 0 0: Single-chip mode...
Page 58 7. Processor Mode M16C/62P Group (M16C/62P, M16C/62PT) Processor Mode Register 1 Symbol Address After Reset 0005h 0X001000b Bit Symbol Bit Name Function 0: 08000h to 26FFFh PM10 CS2 Area Switch Bit (Block A disable) (Data Block Enable Bit) 1: 10000h to 26FFFh...
Page 59 7. Processor Mode M16C/62P Group (M16C/62P, M16C/62PT) PM13=0 Single-Chip Mode Internal RAM Internal ROM 00000h Address XXXXXh Capacity Address YYYYYh Capacity 4 Kbytes 013FFh 48 Kbytes F4000h 00400h 5 Kbytes 017FFh F0000h 64 Kbytes 96 Kbytes 10 Kbytes 02BFFh E8000h...
Page 60 8. Bus M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus Note 8. Bus is described in the M16C/62P (128-pin version and 100-pin version) only as an example. The M16C/62P (80-pin version) and M16C/62PT do not use memory expansion mode, and microprocessor mode.
Page 61: Address Bus
8. Bus M16C/62P Group (M16C/62P, M16C/62PT) 8.2 Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait. 8.2.1 Address Bus The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or 20 bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register.
Page 62 8. Bus M16C/62P Group (M16C/62P, M16C/62PT) Example 1 Example 2 To access the external area indicated by CSj in the next cycle after To access the internal ROM or internal RAM in the next cycle after accessing the external area indicated by CSi...
Page 63 8. Bus M16C/62P Group (M16C/62P, M16C/62PT) 8.2.4 Read and Write Signals _____ When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD, ________ ______ _____ ________ ________ BHE and WR or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When...
Page 64 8. Bus M16C/62P Group (M16C/62P, M16C/62PT) ________ 8.2.6 The RDY Signal This signal is provided for accessing external devices which need to be accessed at low speed. If input ________ on the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in the bus cycle.
Page 65 8. Bus M16C/62P Group (M16C/62P, M16C/62PT) __________ 8.2.7 HOLD Signal This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the __________ input on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in __________ process finishes.
Page 66 8. Bus M16C/62P Group (M16C/62P, M16C/62PT) Table 8.6 Pin Functions for Each Processor Mode Memory Expansion Processor Mode Memory Expansion Mode or Microprocessor Mode Mode 01b(CS2 is for multiplexed bus and 00b(separate bus) 11b (multiplexed others are for separate bus)
Page 67 8. Bus M16C/62P Group (M16C/62P, M16C/62PT) 8.2.9 External Bus Status When Internal Area Accessed Table 8.7 shows the external bus status when the internal area is accessed. Table 8.7 External Bus Status When Internal Area Accessed Item SFR Accessed Internal ROM, RAM Accessed...
Page 68 8. Bus M16C/62P Group (M16C/62P, M16C/62PT) Table 8.8 Bit and Bus Cycle Related to Software Wait CSR Register CSE Register CS3W Bit CSE31W to CSE30W Bit PM2 Register PM1 Register Software Wait CSE21W to CSE20W Bit CS2W Bit Area Bus Mode...
Page 69 8. Bus M16C/62P Group (M16C/62P, M16C/62PT) Figure 8.7 Typical Bus Timings Using Software Wait (1) page 55...
Page 70 8. Bus M16C/62P Group (M16C/62P, M16C/62PT) (1) Separate Bus, 3-Wait Setting Bus cycle Bus cycle BCLK Write signal Read signal Data bus Input Output Address Address Address bus (2) Multiplexed Bus, 1- or 2-Wait Setting Bus cycle Bus cycle BCLK...
Page 71 M16C/62P Group (M16C/62P, M16C/62PT) 9. Memory Space Expansion Function Note 9. Memory Space Expansion Function is described in the M16C/62P (128-pin version and 100-pin version) only as an example. The M16C/62P (80-pin version) and M16C/62PT do not use this function.
Page 72 9. Memory Space Expansion Function M16C/62P Group (M16C/62P, M16C/62PT) Data Bank Register Symbol Address After Reset 000Bh Bit Name Function Bit Symbol Nothing is assigned. When write, set to “0”. When read, its content is (b1-b0) “0”. Offset Bit 0: Not offset...
Page 73 9. Memory Space Expansion Function M16C/62P Group (M16C/62P, M16C/62PT) 0 5 3 0 E T q 3 6 9 3 2 0 7 T j E T 2 2 2 . . T w 7 7 l 1 . 7 9 3 q 3 6 0 S 2 3 F F h...
Page 74 9. Memory Space Expansion Function M16C/62P Group (M16C/62P, M16C/62PT) Memory expansion mode Microprocessor mode 00000h 00400h Internal RAM Internal RAM XXXXX Reserved area Reserved area 04000h (16 Kbytes) 08000h Reserved, external area Reserved, external area (PM10=0: 124 Kbytes) 10000h (PM10=1: 92 Kbytes)
Page 75 9. Memory Space Expansion Function M16C/62P Group (M16C/62P, M16C/62PT) Figure 9.6 shows the external memory connect example in 4-Mbyte mode. _____ _______ In this example, the CS pin of 4-Mbyte ROM is connected to the CS0 pin of microcomputer. The 4 Mbyte...
Page 76 9. Memory Space Expansion Function M16C/62P Group (M16C/62P, M16C/62PT) Memory expansion mode where PM13 =0 ROM address Microcomputer address Output from the Microcomputer Pins Bank Access OFS bit in DBR OFS bit in DBR CS Output Address Output Number Area...
Page 77 9. Memory Space Expansion Function M16C/62P Group (M16C/62P, M16C/62PT) Memory expansion mode where PM13 =1 ROM address Microcomputer address Output from the Microcomputer Pins Bank Access OFS bit in DBR OFS bit in DBR CS Output Address Output Number Area...
Page 78 9. Memory Space Expansion Function M16C/62P Group (M16C/62P, M16C/62PT) Microprocessor mode ROM address Microcomputer address Output from the Microcomputer Pins Bank Access OFS bit in DBR OFS bit in DBR CS Output Address Output Number Area register = 1 register = 0...
Page 79 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generating Circuit 10.1 Types of the Clock Generating Circuit Four circuits are incorporated to generate the system clock signal : • Main clock oscillation circuit • Sub clock oscillation circuit •...
Page 80 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) CM01–CM00=00b Sub-clock I/O ports generating circuit PM01–PM00=00b, CM01–CM00=01b CLKOUT PM01–PM00=00b, CM01–CM00=10b XCIN XCOUT PM01–PM00=00b, CM01–CM00=11b fC32 1/32 CM04 PCLK0=1 Sub-clock PCLK0=0 On-chip On-chip CM21 oscillator oscillator clock Oscillation f1SIO stop, re- PCLK1=1...
Page 81 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) System Clock Control Register 0 Symbol Address After Reset 0006h 01001000b Bit Symbol Function Name b1 b0 CM00 Clock Output Function 0 0 : I/O port P5_7 Select Bit 0 1 : fC output...
Page 82 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) System Clock Control Register 1 Symbol Address After Reset 0007h 00100000b Bit Symbol Function Name All Clock Stop Control Bit 0 : Clock on CM10 (4, 6) 1 : All clocks off (stop mode)
Page 83 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) Oscillation Stop Detection Register Symbol Address After Reset (11) 0X000000b 000Ch Bit Symbol Bit Name Function 0: Oscillation stop, re-oscillation Oscillation Stop, CM20 detection function disabled Re-Oscillation Detection 1: Oscillation stop, re-oscillation...
Page 84 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) Peripheral Clock Select Register Symbol Address When Reset PCLKR 025Eh 00000011b 0 0 0 0 0 0 Bit Name Function Bit Symbol Timers A, B Clock Select PCLK0 0 : f2 Bit (Clock source for...
Page 85 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) (1, 2) PLL Control Register 0 Symbol Address After Reset PLC0 001Ch 0001X010b Bit Name Function Symbol b1b0 PLL Multiplying Factor PLC00 0 0 0: Do not set Select Bit 0 0 1: Multiply by 2...
Page 86: Main Clock
10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) The following describes the clocks generated by the clock generation circuit. 10.1.1 Main Clock This clock is used as the clock source for the CPU and peripheral function clocks. This clock is used as the clock source for the CPU and peripheral function clocks.
Page 87 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) 10.1.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. In addition, an fc clock with the same frequency as that of the sub clock can be output from the CLKOUT pin.
Page 88 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) 10.1.3 On-chip Oscillator Clock This clock, approximately 1MHz, is supplied by a on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1”...
Page 89 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) Using the PLL clock as the clock source for the CPU Set the CM07 bit to “0” (main clock), the CM17 to CM16 bits to “00b”(main clock undivided), and the CM06 bit to “0”...
Page 90 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) 10.2 CPU Clock and Peripheral Function Clock Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions. 10.2.1 CPU Clock and BCLK These are operating clocks for the CPU and watchdog timer.
Page 91 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) 10.4 Power Control Normal operation mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait mode and stop mode, are called normal operation mode in this document.
Page 92 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) 10.4.1.7 On-chip Oscillator Low Power Dissipation Mode The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be selected as in the on-chip oscillator mode. The on-chip oscillator clock is the clock source for the peripheral function clocks.
Page 93 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) Table 10.4 Pin Status During Wait Mode Memory Expansion Mode Single-Chip Mode Microprocessor Mode _______ _______ Does not become a bus A0 to A19, D0 to D15, CS0 to CS3, Retains status before wait mode ________ control pin.
Page 94 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) 10.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode.
Page 95 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) 10.4.3.3 Exiting Stop Mode Table 10.6 Pin Status in Stop Mode Memory Expansion Mode Single-Chip Mode Microprocessor Mode _______ _______ A0 to A19, D0 to D15, CS0 to CS3, Retains status before stop mode...
Page 96 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) Figure 10.10 shows the state transition from normal operation mode to stop mode and wait mode. Figure 10.11 shows the state transition in normal operation mode. Table 10.7 shows a state transition matrix describing allowed transition and setting. The vertical line shows current state and horizontal line shows state after transition.
Page 97 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) Main clock oscillation On-chip oscillator clock oscillation On-chip oscillator low power Middle-speed mode Middle-speed mode Middle-speed mode PLL operation mode Middle-speed mode On-chip oscillator mode dissipation mode (divide by 4) High-speed mode...
Page 98 10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) Table 10.7 Allowed Transition and Setting State after transition On-chip Oscillator High-Speed Mode, Low Power PLL Operation On-chip Oscillator Low Power Stop Mode Wait Mode Low-Speed Mode Middle-Speed Mode Dissipation Mode Mode...
Page 99: System Clock Protection Function
10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) 10.5 System Clock Protection Function The system clock protection function prohibits the CPU clock from changing clock sources when the main clock is selected the CPU clock source. This prevents the CPU clock from stopping should the program crash.
Page 100: Operation When Cm27 Bit = 0 (Oscillation Stop Detection Reset)
10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) 10.6.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) Where main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to 4.
Page 101: How To Use Oscillation Stop And Re-Oscillation Detect Function
10. Clock Generating Circuit M16C/62P Group (M16C/62P, M16C/62PT) 10.6.3 How to Use Oscillation Stop and Re-oscillation Detect Function • The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer interrupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
Page 102: Protection
11. Protection Note 11. Protection is described in the M16C/62P only as an example. The M16C/62PT do not used the PRC3 bit in the PRCR register. In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily.
Page 103: Interrupt
12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt Note 12. Interrupt is described in the M16C/62P (128-pin version and 100-pin version) only as an example. ________ ________ The M16C/62P (80-pin version) do not use INT3 to INT5 interrupt of peripheral function.
Page 104: Software Interrupts
12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) 12.2 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 12.2.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 12.2.2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the operation resulted in an overflow).
Page 105: Hardware Interrupts
12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) 12.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 12.3.1 Special Interrupts Special interrupts are non-maskable interrupts. _______ 12.3.1.1 NMI Interrupt _______ _______ An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details...
Page 106: Interrupts And Interrupt Vector
12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) 12.4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector.
Page 107: Relocatable Vector Tables
12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) 12.4.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 12.2 lists the relocatable vector tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses.
Page 108: Interrupt Control
12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) 12.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Page 109 12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) Interrupt Control Register Symbol Address After Reset TB5IC 0045h XXXXX000b TB4IC/U1BCNIC 0046h XXXXX000b TB3IC/U0BCNIC 0047h XXXXX000b BCNIC 004Ah XXXXX000b DM0IC, DM1IC 004Bh, 004Ch XXXXX000b KUPIC 004Dh XXXXX000b ADIC 004Eh XXXXX000b S0TIC to S2TIC 0051h, 0053h, 004Fh...
Page 110: I Flag
12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) 12.5.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
Page 111: Interrupt Sequence
12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) 12.5.4 Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
Page 112: Interrupt Response Time
12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) 12.5.5 Interrupt Response Time Figure 12.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed.
Page 113: Saving Registers
12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) 12.5.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first.
Page 114 12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP at the time of acceptance of an interrupt request, is even or odd. If the stack pointer is even, the FLG register and the PC are saved,16 bits at a time.
Page 115: Returning From An Interrupt Routine
12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) 12.5.8 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt se- quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Page 116 12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) Priority level of each interrupt Level 0 (initial value) INT1 Highest Timer B2 Timer B0 Timer A3 Timer A1 Timer B4, UART1 bus collision INT3 INT2 INT0 Timer B1 Timer A4 Timer A2 Timer B3, UART0 bus collision...
Page 117 12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) ______ 12.6 INT Interrupt _______ INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi bit in the IFSR register. ________ ________ INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively.
Page 118: Key Input Interrupt
12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) ______ 12.7 NMI Interrupt _______ _______ ______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. _______ The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register.
Page 119: Address Match Interrupt
12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) 12.9 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the ad- dress indicated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi register.
Page 120 12. Interrupt M16C/62P Group (M16C/62P, M16C/62PT) Address Match Interrupt Enable Register Symbol Address After Reset AIER 0009h XXXXXX00b Bit Symbol Bit Name Function Address Match Interrupt 0 0 : Interrupt disabled AIER0 Enable Bit 1 : Interrupt enabled Address Match Interrupt 1...
Page 121: Watchdog Timer
13. Watchdog Timer M16C/62P Group (M16C/62P, M16C/62PT) 13. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom- mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler.
Page 122: Count Source Protective Mode
13. Watchdog Timer M16C/62P Group (M16C/62P, M16C/62PT) Watchdog Timer Control Register b4 b3 Symbol Address After Reset 000Fh 00XXXXXXb Bit Symbol Bit Name Function High-order Bit of Watchdog Timer (b4-b0) Cold Start / Warm Start 0 : Cold Start WDC5...
Page 123: Cold Start / Warm Start
13. Watchdog Timer M16C/62P Group (M16C/62P, M16C/62PT) 13.2 Cold start / Warm start The WDC5 flag in the WDC register indicates the last reset by power on (cold start) or by reset signal (warm start). The WDC5 flag is set “0” at power on, and is set “1” at writing any data to the WDC register. The flag is not set to “0”...
Page 124: Dmac
14. DMAC M16C/62P Group (M16C/62P, M16C/62PT) 14. DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the source address to the destination address.
Page 125 14. DMAC M16C/62P Group (M16C/62P, M16C/62PT) Table 14.1 DMAC Specifications Item Specification No. of Channels 2 (cycle steal method) Transfer Memory Space • From any address in the 1-Mbyte space to a fixed address • From a fixed address to any address in the 1-Mbyte space •...
Page 126 14. DMAC M16C/62P Group (M16C/62P, M16C/62PT) DMA0 Request Cause Select Register Symbol Address After Reset DM0SL 03B8h Bit Symbol Function Bit Name DSEL0 DMA Request Factor (NOTE 1) Select Bit DSEL1 DSEL2 DSEL3 Nothing is assigned. When write, set to “0”.
Page 127 14. DMAC M16C/62P Group (M16C/62P, M16C/62PT) DMA1 Request Cause Select Register Symbol Address After Reset DM1SL 03BAh Bit Name Function Bit Symbol DSEL0 (NOTE 1) DMA Request Factor Select Bit DSEL1 DSEL2 DSEL3 Nothing is assigned. When write, set to “0”.
Page 128 14. DMAC M16C/62P Group (M16C/62P, M16C/62PT) DMAi Source Pointer (i = 0, 1) (b19) (b16)(b15) (b8) (b23) Symbol Address After Reset SAR0 0022h to 0020h Indeterminate SAR1 0032h to 0030h Indeterminate Setting Range Function Set the source address of transfer 00000h to FFFFFh Nothing is assigned.
Page 129: Transfer Cycles
14. DMAC M16C/62P Group (M16C/62P, M16C/62PT) 14.1 Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer.
Page 130 14. DMAC M16C/62P Group (M16C/62P, M16C/62PT) (1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address BCLK Address Dummy CPU use Source Destination CPU use cycle RD signal WR signal Data...
Page 131: Dma Transfer Cycles
14. DMAC M16C/62P Group (M16C/62P, M16C/62PT) 14.2 DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 14.2 shows the number of DMA transfer cycles. Table 14.3 shows the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No.
Page 132: Dma Enable
14. DMAC M16C/62P Group (M16C/62P, M16C/62PT) 14.3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to “1” (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register is “1”...
Page 133: Channel Priority And Dma Transfer Timing
14. DMAC M16C/62P Group (M16C/62P, M16C/62PT) 14.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are de- tected active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel is set to “1”...
Page 134 M16C/62P Group (M16C/62P, M16C/62PT)
Page 135: Timers
15. Timers M16C/62P Group (M16C/62P, M16C/62PT) Timer B2 overflow or underflow (to a count source of the timer A) TCK1 to TCK0 00: Timer mode 10: Pulse period / pulse width measurement mode TMOD1 to TMOD0 Timer B0 interrupt Timer B0...
Page 136 M16C/62P Group (M16C/62P, M16C/62PT)
Page 137: Timer A
15. Timers M16C/62P Group (M16C/62P, M16C/62PT) Timer Ai Mode Register (i=0 to 4) Symbol Address After Reset TA0MR to TA4MR 0396h to 039Ah Bit Name Function Symbol TMOD0 b1 b0 Operation Mode Select Bit 0 0 : Timer mode 0 1 : Event counter mode...
Page 138 M16C/62P Group (M16C/62P, M16C/62PT)
Page 139 15. Timers M16C/62P Group (M16C/62P, M16C/62PT) One-Shot Start Flag Symbol Address After Reset ONSF 0382h Bit Symbol Bit Name Function Timer A0 One-Shot Start Flag TA0OS The timer starts counting by setting this bit to “1” while the TMOD1 to...
Page 140 M16C/62P Group (M16C/62P, M16C/62PT)
Page 141: Event Counter Mode
15. Timers M16C/62P Group (M16C/62P, M16C/62PT) 15.1.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 15.2 lists specifications in event counter mode (when not processing two-phase pulse signal).
Page 142 M16C/62P Group (M16C/62P, M16C/62PT)
Page 143 15. Timers M16C/62P Group (M16C/62P, M16C/62PT) Table 15.3 Specifications in Event Counter Mode (when processing two-phase pulse signal with Timers A2, A3 and A4) Item Specification Count Source • Two-phase pulse signals input to TAiIN or TAiOUT pins (i = 2 to 4) Count Operation •...
Page 144 M16C/62P Group (M16C/62P, M16C/62PT)
Page 145 15. Timers M16C/62P Group (M16C/62P, M16C/62PT) 15.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two- phase pulse signal processing. This function can only be used in Timer A3 event counter mode during two-phase pulse signal pro- cessing, free-running type, x4 processing, with Z-phase entered from the ZP pin.
Page 146: One-Shot Timer Mode
M16C/62P Group (M16C/62P, M16C/62PT)
Page 147 15. Timers M16C/62P Group (M16C/62P, M16C/62PT) Timer Ai Mode Register (i=0 to 4) Symbol Address After Reset TA0MR to TA4MR 0396h to 039Ah Bit Symbol Bit Name Function TMOD0 Operation Mode b1 b0 1 0 : One-shot timer mode Select Bit...
Page 148: Pulse Width Modulation (Pwm) Mode
M16C/62P Group (M16C/62P, M16C/62PT)
Page 149 15. Timers M16C/62P Group (M16C/62P, M16C/62PT) Timer Ai Mode Register (i= 0 to 4) Symbol Address After Reset TA0MR to TA4MR 0396h to 039Ah Bit Symbol Bit Name Function b1 b0 TMOD0 Operation Mode 1 1 : PWM mode Select Bit...
Page 150 M16C/62P Group (M16C/62P, M16C/62PT)
Page 151: Timer B
M16C/62P Group (M16C/62P, M16C/62PT) 15.2 Timer B Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TB1IN pin of Timer [Precautions when using Timer B1] • Event Counter Mode The external input signals cannot be counted. Set the TCK1 bit in the TB1MR register to “1”...
Page 152 15. Timers M16C/62P Group (M16C/62P, M16C/62PT) Timer Bi Mode Register (i=0 to 5) Symbol Address After Reset TB0MR to TB2MR 039Bh to 039Dh 00XX0000b TB3MR to TB5MR 035Bh to 035Dh 00XX0000b Bit Symbol Function Name TMOD0 b1 b0 Operation Mode Select Bit...
Page 153 15. Timers M16C/62P Group (M16C/62P, M16C/62PT) Count Start Flag Symbol Address After Reset TABSR 0380h Bit Symbol Bit Name Function TA0S Timer A0 Count Start Flag 0 : Stops counting 1 : Starts counting TA1S Timer A1 Count Start Flag...
Page 154: Timer Mode
15. Timers M16C/62P Group (M16C/62P, M16C/62PT) 15.2.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 15.6). Figure 15.18 shows TBiMR register in timer mode. Table 15.6 Specifications in Timer Mode Item Specification Count Source...
Page 155: Event Counter Mode
15. Timers M16C/62P Group (M16C/62P, M16C/62PT) 15.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 15.7). Figure 15.19 shows TBiMR register in event counter mode.
Page 156: Pulse Period And Pulse Width Measurement Mode
15. Timers M16C/62P Group (M16C/62P, M16C/62PT) 15.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see Table 15.8). Figure 15.20 shows TBiMR register in pulse period and pulse width measurement mode.
Page 157 15. Timers M16C/62P Group (M16C/62P, M16C/62PT) Count source “H” Measurement pulse “L” Transfer (indeterminate value) (NOTE 1) (NOTE 1) Timing at which counter reaches “0000h” TBiS bit “0” IR bit in “1” TBiIC register “0” “1” MR3 bit in TBiMR register “0”...
Page 158: Three-Phase Motor Control Timer Function
100 pin version) and M16C/62PT (100 pin version) only as an example. The M16C/62P (80 pin version) and M16C/62PT (80 pin version) do not use this function. Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 16.1 lists the specifications of the three-phase motor control timer function.
Page 160 16. Three-Phase Motor Control Timer Function M16C/62P Group (M16C/62P, M16C/62PT) Three-Phase PWM Control Register 0 Symbol Address After Reset INVC0 0348h Bit Name Function Symbol 0: The ICTB2 counter is incremented by one on the rising edge of the timer A1 reload control signal...
Page 161 16. Three-Phase Motor Control Timer Function M16C/62P Group (M16C/62P, M16C/62PT) Three-Phase PWM Control Register 1 Symbol Address After Reset INVC1 0349h Bit Name Function Symbol 0: Timer B2 underflow Timer A1, A2 and A4 INV10 1: Timer B2 underflow and write to...
Page 162 16. Three-Phase Motor Control Timer Function M16C/62P Group (M16C/62P, M16C/62PT) Three-Phase Output Buffer Register i (i=0, 1) Symbol Address After Reset IDB0, IDB1 034Ah, 034Bh Bit Name Function Symbol U-Phase Output Buffer i Write output level 0: Active level DUBi...
Page 163 16. Three-Phase Motor Control Timer Function M16C/62P Group (M16C/62P, M16C/62PT) (1, 2, 3) Timer B2 Interrupt Generation Frequency Set Counter Symbol Address After Reset ICTB2 034Dh Indeterminate Setting Range Function When the INV01 bit is set to “0” (the ICTB2 counter...
Page 164 16. Three-Phase Motor Control Timer Function M16C/62P Group (M16C/62P, M16C/62PT) Timer B2 Register Symbol Address After Reset 0395h - 0394h Indeterminate Setting Range Function If setting value is n, count source is divided by n+1. 0000h to FFFFh The timers A1, A2 and A4 start every time an underflow occurs.
Page 165 16. Three-Phase Motor Control Timer Function M16C/62P Group (M16C/62P, M16C/62PT) Timer Ai Mode Register (i=1, 2, 4) Symbol Address After Reset TA1MR, TA2MR, TA4MR 0397h, 0398h, 039Ah Bit Name Function Symbol Set to “10b” (one-shot timer TMOD0 Operation Mode mode) with the three-phase motor...
Page 166 16. Three-Phase Motor Control Timer Function M16C/62P Group (M16C/62P, M16C/62PT) The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to “1”. When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to control three-phase PWM outputs (U, U, V, V, W and W).
Page 167 16. Three-Phase Motor Control Timer Function M16C/62P Group (M16C/62P, M16C/62PT) Sawtooth Waveform as a Carrier Wave Sawtooth Wave Signal Wave Timer B2 Timer A4 Start Trigger Signal Timer A4 One-Shot Pulse Rewrite the IDB0 Transfer the counter to the and IDB1 registers...
Page 168: Serial I/O
M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial I/O Note 17. Serial I/O is described in the M16C/62P (128-pin version and 100-pin version) and the M16C/ 62PT (100-pin version) only as an example. _________ The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include CLK2, CTS2/ _________ RTS2, SIN3 pins.
Page 169 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) PCLK1 f1SIO or f2SIO (UART0) TXD0 RXD polarity RXD0 reversing circuit UART reception Transmit/ 1/16 receive Clock source selection Clock synchronous unit type CLK1 to CLK0 CKDIR Internal U0BRG f1SIO or f2SIO register...
Page 170 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) PCLK1 f2SIO f1SIO or f2SIO f1SIO Main clock, PLL clock, or on-chip oscillator clock f8SIO f32SIO (UART2) TXD2 RXD polarity reversing polarity RXD2 circuit reversing UART reception SMD2 to SMD0 Transmit/ circuit 010, 100, 101, 110...
Page 171 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) IOPOL No reverse RXDi RXD data reverse circuit Reverse Clock synchronous type UART (7 bits) PRYE UART Clock STPS (8 bits) synchronous UART(7 bits) type UARTi receive register disabled UART Clock enabled UART...
Page 172 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) UARTi Transmit Buffer Register (i=0 to 2) Symbol Address After Reset (b15) (b8) U0TB 03A3h to 03A2h Indeterminate U1TB 03ABh to 03AAh Indeterminate U2TB 037Bh to 037Ah Indeterminate Function Transmit data Nothing is assigned. When write, set to “0”.
Page 173 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) UARTi Transmit/Receive Mode Register (i=0 to 2) Symbol Address After Reset U0MR to U2MR 03A0h, 03A8h, 0378h Function Bit Name Symbol b2 b1 b0 Serial I/O Mode Select SMD0 0 0 0 : Serial I/O disabled...
Page 174 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) UARTi Transmit/Receive Control Register 1 (i=0, 1) Symbol Address After Reset U0C1, U1C1 03A5h, 03ADh 00XX0010b Function Bit Name Symbol Transmit Enable Bit 0 : Transmission disabled 1 : Transmission enabled Transmit Buffer...
Page 175 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) UART Transmit/Receive Control Register 2 Symbol Address After Reset UCON 03B0h X0000000b Function Bit Name Symbol U0IRS UART0 Transmit Interrupt 0 : Transmit buffer empty (Tl = 1) Cause Select Bit 1 : Transmission completed (TXEPT = 1)
Page 176 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) UARTi Special Mode Register 2 (i=0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset U0SMR2 to U2SMR2 036Eh, 0372h, 0376h X0000000b Bit Name Function Symbol C Mode Select Bit 2 See Table 17.12 I...
Page 177 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) UARTi Special Mode Register 4 (i=0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset U0SMR4 to U2SMR4 036Ch, 0370h, 0374h Bit Name Function Symbol Start Condition 0 : Clear...
Page 178: Clock Synchronous Serial I/O Mode
17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.1 Clock Synchronous serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 17.1 lists the specifications of the clock synchronous serial I/O mode. Table 17.2 lists the registers used in clock synchronous serial I/O mode and the register values set.
Page 179 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Table 17. 2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Function UiTB 0 to 7 Set transmission data UiRB 0 to 7 Reception data can be read...
Page 180 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Table 17.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 17.3 shows pin functions for the case where the multiple transfer clock output pin select function is dese- lected.
Page 181 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) (1) Example of Transmit Timing (when internal clock is selected) Transfer clock “1”0 UiC1 register “0” Write data to the UiTB register TE bit “1” UiC1 register TI bit “0” “H” TCLK “L”...
Page 182 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below. • Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to “0”...
Page 183 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 17.11 shows the transfer format. (1) When the UFORM bit in the UiC0 register = 0 (LSB first)
Page 184 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.1.5 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register.
Page 185 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) _______ _______ 17.1.1.7 CTS/RTS Function _______ ________ When the CTS function is used transmit and receive operation start when “L” is applied to the CTSi/ ________ ________ ________ RTSi (i=0 to 2) pin. Transmit and receive operation begins when the CTSi/RTSi pin is held “L”. If the “L”...
Page 186: Clock Asynchronous Serial I/O (Uart) Mode
17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 17.5 lists the specifications of the UART mode.
Page 187 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Table 17.6 Registers to Be Used and Settings in UART Mode Register Function UiTB 0 to 8 Set transmission data UiRB 0 to 8 Reception data can be read OER,FER,PER,SUM Error flag UiBRG...
Page 188 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Table 17.7 lists the functions of the input/output pins during UART mode. Table 17.8 lists the P6_4 pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TXDi pin outputs an “H”...
Page 189 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to “L”. Transfer clock UiC1 register “1”...
Page 190 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) • Example of Receive Timing when Transfer Data is 8 Bits Long (parity disabled, one stop bit) UiBRG count source “1” UiC1 register RE bit “0” Stop bit Start bit RXDi Sampled “L”...
Page 191 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.2.2 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below. • Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to “0” (reception disabled) (2) Set the RE bit in the UiC1 register to “1”...
Page 192 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.2.4 Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 17.18 shows serial data logic.
Page 193 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) _______ _______ 17.1.2.6 CTS/RTS Function _______ ________ ________ When the CTS function is used transmit operation start when “L” is applied to the CTSi/RTSi (i=0 to 2) ________ ________ pin. Transmit operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal is switched to “H”...
Page 194: Special Mode 1 (I2C Mode)
M16C/62P Group (M16C/62P, M16C/62PT)
Page 195 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Start and stop condition generation block SDAi DMA0, DMA1 request STSPSEL=1 (UART1: DMA0 only) SDA(STSP) Delay circuit SCL(STSP) STSPSEL=0 IICM2=1 Transmission UARTi transmit, register NACK interrupt ACK=1 ACK=0 request IICM=1 and UARTi IICM2=0...
Page 196 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Table 17. 11 Registers to Be Used and Settings in I C Mode (1) (Continued) Register Function Master Slave UiTB 0 to 7 Set transmission data Set transmission data UiRB 0 to 7...
Page 197 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Table17.12 Registers to Be Used and Settings in I C Mode (2) (Continued) Register Function Master Slave UiSMR4 STAREQ Set this bit to “1” to generate start Set to “0” condition RSTAREQ Set this bit to “1” to generate restart Set to “0”...
Page 198 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Table 17.13 I C Mode Functions Clock Synchronous Serial I/O Function C Mode (SMD2 to SMD0 = 010b, IICM = 1) Mode (SMD2 to SMD0 = 001b, IICM2 = 0 IICM2 = 1...
Page 199 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) (1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay) SCLi D8 (ACK, NACK) SDAi ACK interrupt (DMA1 request), NACK interrupt Transfer to UiRB register (3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0...
Page 200 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state.
Page 201 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Table 17.14 STSPSEL Bit Functions Function STSPSEL = 0 STSPSEL = 1 Output of SCLi and SDAi Pins Output of transfer clock and Output of a start/stop condition data according to the STAREQ,...
Page 202 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 17.22 Transfer to UiRB Register and Interrupt Timing. The CSC bit in the UiSMR2 register is used to synchronize the internally generated clock (internal SCLi) and an external clock supplied to the SCLi pin.
Page 203 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.3.7 ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and the ACKC bit in the UiSMR4 register is se to “1” (ACK data output), the value of the ACKD bit in the UiSMR4 register is output from the SDAi pin.
Page 204: Special Mode 2
17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.4 Special Mode 2 Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 17.15 lists the specifications of Special Mode 2. Table 17.16 lists the registers used in Special Mode 2 and the register values set.
Page 205 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) P1_3 P1_2 P9_3 P7_2(CLK2) P7_2(CLK2) P7_1(RXD2) P7_1(RXD2) P7_0(TXD2) P7_0(TXD2) Microcomputer Microcomputer (Master) (Slave) P9_3 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) Microcomputer (Slave) Figure 17.25 Serial Bus Communication Control Example (UART2) page 191...
Page 206 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Table 17. 16 Registers to Be Used and Settings in Special Mode 2 Register Function UiTB 0 to 7 Set transmission data UiRB 0 to 7 Reception data can be read Overrun error flag...
Page 207 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the UiSMR3 register and the CKPOL bit in the UiC0 register.
Page 208 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Slave control input Clock input (CKPOL=0, CKPH=0) Clock input (CKPOL=1, CKPH=0) Data output timing Data input timing Figure 17.27 Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock) Figure 17.28 Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)
Page 209: Special Mode 3 (Ie Mode)
17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.5 Special Mode 3 (IE mode) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform. Table 17.17 lists the registers used in IE mode and the register values set. Figure 17.29 shows the functions of bus collision detect function related bits.
Page 210 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) (1) The ABSCS Bit in the UiSMR Register (Bus collision detect sampling clock select) (i=0 to 2) If ABSCS=0, bus collision is determined at the rising edge of the transfer clock Transfer clock...
Page 211: Special Mode 4 (Sim Mode) (Uart2)
17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected.
Page 212 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Table 17. 19 Registers to Be Used and Settings in SIM Mode Register Function U2TB 0 to 7 Set transmission data U2RB 0 to 7 Reception data can be read OER,FER,PER,SUM Error flag...
Page 213 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) (1) Transmission Transfer clock “1” U2C1 register TE bit Write data to U2TB register “0” “1” U2C1 register TI bit “0” Transferred from U2TB register to UART2 transmit register Parity Stop Start TXD2...
Page 214 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Microcomputer SIM card TXD2 RXD2 Figure 17.31 SIM Interface Connection 17.1.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to “1”. The parity error signal is output when a parity error is detected while receiving data. This is achieved by pulling the TXD2 output low with the timing shown in Figure 17.32.
Page 215 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.1.6.2 Format When direct format, set the PRY bit in the U2MR register to “1,” UFORM bit in the U2C0 register to “0” and U2LCH bit in the U2C1 register to “0”. When inverse format, set the PRY bit to “0,” UFORM bit to “1” and U2LCH bit to “1”.
Page 216: Si/O3 And Si/O4
M16C/62P Group (M16C/62P, M16C/62PT) 17.2 SI/O3 and SI/O4 Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include SIN3 pin of SI/O3. SI/O3 is only for transmission. Reception is impossible. SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os.
Page 217 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) S I/Oi Control Register (i = 3, 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0362h 01000000b 0366h 01000000b Bit Name Description Symbol b1 b0 SMi0 Internal Synchronous...
Page 218 17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) Table 17.20 SI/O3 and SI/O4 Specifications Item Specification Transfer Data Format • Transfer data length: 8 bits Transfer Clock • SMi6 bit in SiC (i=3, 4) register = 1 (internal clock) : fj/ 2(n+1) fj = f1SIO, f8SIO, f32SIO.
Page 219: Si/Oi Operation Timing
17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.2.1 SI/Oi Operation Timing Figure 17.36 shows the SI/Oi operation timing. 1.5 cycle (max.) "H" SI/Oi internal clock "L" "H" CLKi output "L" Signal written to the "H" "L" SiTRR register (NOTE 2) SOUTi output "H"...
Page 220: Functions For Setting An Souti Initial Value
17. Serial I/O M16C/62P Group (M16C/62P, M16C/62PT) 17.2.3 Functions for Setting an S i Initial Value If the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output can be fixed high or low when not transferring. Figure 17.38 shows the timing chart for setting an SOUTi initial value and how to set it.
Page 221: A/D Converter
18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10_0 to P10_7, ___________ P9_5, P9_6, P0_0 to P0_7, and P2_0 to P2_7. Similarly, ADTRG input shares the pin with P9_7. Therefore, when using these inputs, make sure the corresponding port direction bits are set to “0”...
Page 222 18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) CKS1 A/D conversion rate selection CKS2 ø Software trigger A/D trigger ADTRG VREF Resistor ladder AVSS VCUT Successive conversion register ADCON1 register ADCON0 register AD0 register (16) AD1 register (16) AD2 register (16)
Page 223 18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) A/D Control Register 0 Symbol Address After Reset ADCON0 03D6h 00000XXXb Bit Symbol Bit Name Function Analog Input Pin Function varies with each operation mode Select Bit b4 b3 A/D Operation Mode 0 0 : One-shot mode...
Page 224 18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) A/D Control Register 2 Symbol Address After Reset ADCON2 03D4h Bit Symbol Function Name 0 : Without sample and hold A/D Conversion Method 1 : With sample and hold Select Bit b2 b1...
Page 225: Mode Description
18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) 18.1 Mode Description 18.1.1 One-Shot Mode In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 18.2 shows the specifications of one-shot mode. Figure 18.4 shows the ADCON0 to ADCON1 registers in one-shot mode.
Page 226 18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) A/D Control Register 0 Symbol Address After Reset ADCON0 03D6h 00000XXXb Bit Symbol Bit Name Function b2 b1 b0 Analog Input Pin 0 0 0 : AN0 is selected Select Bit 0 0 1 : AN1 is selected...
Page 227: Repeat Mode
18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) 18.1.2 Repeat mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 18.3 shows the specifications of repeat mode. Figure 18.5 shows the ADCON0 to ADCON1 registers in repeat mode.
Page 228 18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) A/D Control Register 0 Symbol Address After Reset ADCON0 03D6h 00000XXXb Bit Symbol Bit Name Function b2 b1 b0 Analog Input Pin 0 0 0 : AN0 is selected Select Bit 0 0 1 : AN1 is selected...
Page 229: Single Sweep Mode
18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) 18.1.3 Single Sweep Mode In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code. Table 18.4 shows the specifications of single sweep mode. Figure 18.6 shows the ADCON0 to ADCON1 registers in single sweep mode.
Page 230 18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) A/D Control Register 0 Symbol Address After Reset ADCON0 03D6h 00000XXXb Bit Symbol Bit Name Function Analog Input Pin Invalid in single sweep mode Select Bit b4 b3 A/D Operation Mode 1 0 : Single sweep mode...
Page 231: Repeat Sweep Mode 0
18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) 18.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code. Table 18.5 shows the specifications of repeat sweep mode 0. Figure 18.7 shows the ADCON0 to ADCON1 registers in repeat sweep mode 0.
Page 232 18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) A/D Control Register 0 Symbol Address After Reset ADCON0 03D6h 00000XXXb Bit Symbol Bit Name Function Analog Input Pin Invalid in repeat sweep mode 0 Select Bit b4 b3 A/D Operation Mode 1 1 : Repeat sweep mode 0 or...
Page 233: Repeat Sweep Mode 1
18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) 18.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltage selectively applied to all pins is repeatedly converted to a digital code. Table 18.6 shows the specifications of repeat sweep mode 1. Figure 18.8 shows the ADCON0 to ADCON1 registers in repeat sweep mode 1.
Page 234 18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) A/D Control Register 0 Symbol Address After Reset ADCON0 03D6h 00000XXXb Bit Symbol Bit Name Function Analog Input Pin Invalid in repeat sweep mode 1 Select Bit b4 b3 A/D Operation Mode 1 1 : Repeat sweep mode 0 or...
Page 235: Function
18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) 18.2 Function 18.2.1 Resolution Select Function The desired resolution can be selected using the BITS bit in the ADCON1 register. If the BITS bit is set to “1” (10-bit conversion accuracy), the A/D conversion result is stored in the bit 0 to bit 9 in the ADi register (i = 0 to 7).
Page 236: Current Consumption Reducing Function
18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) 18.2.5 Current Consumption Reducing Function When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be separated using the VCUT bit in the ADCON1 register. When separated, no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
Page 237 18. A/D Converter M16C/62P Group (M16C/62P, M16C/62PT) Microcomputer Sensor equivalent circuit R (7.8kΩ) Sampling time C (1.5pF) Sample and hold function enabled: Sample and hold function disabled: Figure 18.10 Analog Input Pin and External Sensor Equivalent Circuit page 223...
Page 238: D/A Converter
19. D/A Converter M16C/62P Group (M16C/62P, M16C/62PT) 19. D/A Converter This is an 8-bit, R-2R type D/A converter. These are two independent D/A converters. D/A conversion is performed by writing to the DAi register (i = 0 to 1). To output the result of conversion, set the DAiE bit in the DACON register to “1”...
Page 239 19. D/A Converter M16C/62P Group (M16C/62P, M16C/62PT) D/A Control Register Symbol Address After Reset DACON 03DCh Bit Symbol Bit Name Function 0 : Output disabled DA0E D/A0 Output Enable Bit 1 : Output enabled 0 : Output disabled DA1E D/A1 Output Enable Bit 1 : Output enabled Nothing is assigned.
Page 240: Crc Calculation
20. CRC Calculation M16C/62P Group (M16C/62P, M16C/62PT) 20. CRC Calculation The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X + 1) to generate CRC code. The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8 bit units.
Page 241 20. CRC Calculation M16C/62P Group (M16C/62P, M16C/62PT) Setup procedure and CRC operation when generating CRC code “80C4h” · CRC operation performed by the M16C CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is...
Page 242: Programmable I/O Ports
There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in the M16C/62P (80-pin version) and the M16C/62PT (80-pin version). Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
Page 243: Port Pi Direction Register (Pdi Register, I = 0 To 13)
21. Programmable I/O Ports M16C/62P Group (M16C/62P, M16C/62PT) 21.1 Port Pi Direction Register (PDi Register, i = 0 to 13) Figure 21.7 shows the direction registers. This register selects whether the I/O port is to be used for input or output. The bits in this register corre- spond one for one to each port.
Page 244 21. Programmable I/O Ports M16C/62P Group (M16C/62P, M16C/62PT) Pull-up selection Direction register P0_0 to P0_7, (inside dotted-line P2_0 to P2_7 included) Data bus Port latch P3_0 to P3_7, (NOTE 1) P4_0 to P4_7, P5_0 to P5_4, P5_6, (inside dotted-line P11_0 to P11_7...
Page 245 21. Programmable I/O Ports M16C/62P Group (M16C/62P, M16C/62PT) Figure 21.2 I/O Ports (2) page 231...
Page 246 21. Programmable I/O Ports M16C/62P Group (M16C/62P, M16C/62PT) Pull-up selection Direction register P6_2, P6_6 Port latch Data bus (NOTE 1) Switching between CMOS and Nch Input to respective peripheral functions Pull-up selection Direction register P6_3, P6_7 “1” Output Port latch...
Page 247 21. Programmable I/O Ports M16C/62P Group (M16C/62P, M16C/62PT) Figure 21.4 I/O Ports (4) page 233...
Page 248 21. Programmable I/O Ports M16C/62P Group (M16C/62P, M16C/62PT) Pull-up selection Direction register P8_7 Data bus Port latch (NOTE 1) Pull-up selection Direction register P8_6 "1" Output Data bus Port latch (NOTE 1) NOTES: Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC.
Page 249 21. Programmable I/O Ports M16C/62P Group (M16C/62P, M16C/62PT) (1, 2, 3) Port Pi Direction Register (i=0 to 7 and 9 to 13) Symbol Address After Reset PD0 to PD3 03E2h, 03E3h, 03E6h, 03E7h PD4 to PD7 03EAh, 03EBh, 03EEh, 03EFh...
Page 250 21. Programmable I/O Ports M16C/62P Group (M16C/62P, M16C/62PT) (2, 3) Port Pi Register (i=0 to 7 and 9 to 13) Symbol Address After Reset P0 to P3 03E0h, 03E1h, 03E4h, 03E5h Indeterminate P4 to P7 03E8h, 03E9h, 03ECh, 03EDh Indeterminate...
Page 251 21. Programmable I/O Ports M16C/62P Group (M16C/62P, M16C/62PT) Port P14 Control Register (128-Pin Package) Symbol Address After Reset PC14 03DEh XX00XXXXb Bit Symbol Bit Name Function The pin level on any I/O port which is set for input mode can be read by...
Page 252 21. Programmable I/O Ports M16C/62P Group (M16C/62P, M16C/62PT) Pull-up Control Register 0 Symbol Address After Reset PUR0 03FCh Bit Symbol Bit Name Function PU00 P0_0 to P0_3 Pull-Up 0 : Not pulled high PU01 P0_4 to P0_7 Pull-Up 1 : Pulled high...
Page 253 21. Programmable I/O Ports M16C/62P Group (M16C/62P, M16C/62PT) Port Control Register Symbpl Address After Reset 03FFh Bit Symbol Bit Name Function PCR0 Port P1 Control Bit Operation performed when the P1 register is read 0: When the port is set for input, the input levels of P10 to P17 pins are read.
Page 254 21. Programmable I/O Ports M16C/62P Group (M16C/62P, M16C/62PT) Table 21.2 Unassigned Pin Handling in Single-chip Mode Pin Name Connection After setting for input mode, connect every pin to VSS via a resistor (pull-down); Ports P0 to P7, (1, 2, 3, 5) P8_0 to P8_4, P8_6 to P8_7, or after setting for output mode, leave these pins open.
Page 255 21. Programmable I/O Ports M16C/62P Group (M16C/62P, M16C/62PT) Microcomputer Microcomputer Port P0 to P14 Port P6 to P14 (Input mode) (Input mode) · · (except for P8_5) · (except for P8_5) · · · · · · · · ·...
Page 256: Flash Memory Version
22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version Aside from the built-in flash memory, the flash memory version microcomputer has the same functions as the masked ROM version. In the flash memory version, the flash memory can perform in three rewrite modes: CPU rewrite mode, stan- dard serial I/O mode and parallel I/O mode.
Page 257 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) Table 22.2 Flash Memory Rewrite Modes Overview Flash Memory CPU rewrite Mode Standard Serial I/O Mode Parallel I/O Mode Rewrite Mode Function The User ROM area is The user ROM area is...
Page 258: Memory Map
22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.1 Memory Map The flash memory contains the user ROM area and the boot ROM area. The user ROM area has space to store the microcomputer operating program in single-chip mode or memory expansion mode and a sepa- rate 4-Kbyte space as the block A.
Page 259: Boot Mode
22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.1.1 Boot Mode The microcomputer enters boot mode when a hardware reset occurs while an “H” signal is applied to the CNVSS and P5_0 pins and an “L” signal is applied to the P5_5 pin. A program in the boot ROM area is executed.
Page 260 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) ROM Code Protect Control Address Symbol Address Value When Shipped ROMCP 0FFFFFh Bit Name Function Bit Symbol Reserved Bit Set to “1” (b0) Reserved Bit Set to “1” (b1) Reserved Bit Set to “1”...
Page 261: Cpu Rewrite Mode
22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.3 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. The user ROM area can be rewritten with the microcomputer mounted on a board without using a parallel or serial programmer.
Page 262: Ew0 Mode
22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.3.1 EW0 Mode The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR11 bit in the FMR1 register to “0”.
Page 263 Flash Module Type FIDR0 0 0: M16C/62N, M3062GF8N type flash module Identification Value 1 0: M16C/62P type flash module FIDR1 1 1: M16C/62M, M16C/62A type flash module Nothing is assigned. (b7-b2) When write, set to “0”. When read, their contents are indeterminate.
Page 264 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.3.3.1 FMR00 Bit This bit indicates the flash memory operating state. It is set to “0” while the program, block erase, erase all unlocked block, lock bit program, or read lock bit status command is being executed; other- wise, it is set to “1”.
Page 265 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) Procedure to Enter EW0 Mode Rewrite control program In boot mode only Single-chip mode, memory expansion mode or boot mode Set the FMR05 bit to “1” (user ROM area accessed) Transfer the rewrite control program in CPU Set the FMR01 bit to “1”...
Page 266 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) Procedure to Enter EW1 Mode Program in the ROM Single-chip mode Set the CM0, CM1, PM1 registers Set the FMR01 bit to “1” (CPU rewrite mode enabled) after writing “0” Set the FMR11 bit to “1” (EW1 mode) after writing "0"...
Page 267 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) Low-power consumption mode program Transfer the low-power consumption mode program Set the FMR01 bit to “1” after setting it to “0” to a space other than the flash memory (CPU rewrite mode enabled) Set the FMSTP bit to “1”...
Page 268: Precautions On Cpu Rewrite Mode
22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.3.4 Precautions on CPU Rewrite Mode 22.3.4.1 Operating Speed Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to a CPU clock frequency of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to “1”...
Page 269 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.3.4.9 Writing Command and Data Write commands and data to even addresses in the user ROM area. 22.3.4.10 Wait Mode When entering wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing the WAIT instruction.
Page 270: Software Commands
22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.3.5 Software Commands Software commands are described below. The command code and data must be read and written in 16- bit units, to and from even addresses in the user ROM area. When writing command code, the 8 high- order bits (D15 to D8) are ignored.
Page 271 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.3.5.4 Program Command (40h) The program command writes 2-byte data to the flash memory. By writing “xx40h” in the first bus cycle and data to the write address in the second bus cycle, an auto program operation (data program and verify) will start.
Page 272 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) Start Write “xxD0h” to the highest- order block address page 258...
Page 273 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.3.5.6 Erase All Unlocked Block The erase all unlocked block command erases all blocks except the block A. By writing “xxA7h” in the first bus cycle and “xxD0h” in the second bus cycle, an auto erase (erase and verify) operation will run continuously in all blocks except the block A.
Page 274 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.3.5.8 Read Lock Bit Status Command (71h) The read lock bit status command reads the lock bit state of a specified block. By writing “xx71h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the second bus cycle, the FMR16 bit in the FMR1 register stores information on whether or not the lock bit of a specified block is locked.
Page 275: Data Protect Function
í 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.3.6 Data Protect Function Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit to “0” (lock bit enabled). The lock bit allows each block to be individually protected (locked) against program and erase.
Page 276 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) Table 22.5 Status Register Bit in Bits in Value Definition FMR0 Status after Status Name Register Register “0” “1” Reset SR7 (D7) FMR00 Sequencer status Busy Ready SR6 (D6) Reserved SR5 (D5)
Page 277: Full Status Check
22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.3.8 Full Status Check If an error occurs when a program or erase operation is completed, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating a specific error. Therefore, execution results can be confirmed by checking these bits (full status check).
Page 278 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) Full status check FMR06 =1 (1) Execute the clear status register command and set the SR4 and SR5 Command bits to “0” (completed as expected) . FMR07=1? sequence error (2) Rewrite command and execute again.
Page 279: Standard Serial I/O Mode
M16C/62P Group (M16C/62P, M16C/62PT) 22.4 Standard Serial I/O Mode In standard serial I/O mode, the serial programmer supporting the M16C/62P (M16C/62P, M16C/62PT) group can be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board.
Page 280 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) Table 22.7 Pin Functions (Flash Memory Standard Serial I/O Mode) Power Name Description Supply Apply the voltage guaranteed for Program and Erase to VCC1 pin VCC1, VCC2, Power Input and VCC2 to the VCC2 pin. The VCC apply condition is that VCC2 VCC1.
Page 281 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) M16C/62P Group (M16C/62P) Flash Memory Version BUSY SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30...
Page 282 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) Flash Memory Version BUSY SCLK 1 00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30...
Page 283 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) Flash Memory Version BUSY SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25...
Page 284 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) Flash Memory Version BUSY SCLK 9 10 11 12 13 14 15 16 17 18 19 20 Mode setup method Value Signal CNVSS VCC1 RESET VSS to VCC...
Page 285: Example Of Circuit Application In The Standard Serial I/O Mode
22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) 22.4.2 Example of Circuit Application in the Standard Serial I/O Mode Figure 22.17 and 22.18 show example of circuit application in standard serial I/O mode 1 and mode 2, respectively. Refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer.
Page 286 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) Microcomputer P6_5/CLK1 P5_0(CE) TXD output P6_7/TXD1 P5_5(EPM) Monitor output P6_4/RTS1 RXD intput CNVSS P6_6/RXD1 Reset input RESET P8_5/NMI User reset signal NOTES: 1. In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVSS input with a switch.
Page 287: Parallel I/O Mode
In parallel I/O mode, the user ROM area and the boot ROM area can be rewritten by a parallel programmer supporting the M16C/62P Group (M16C/62P, M16C/62PT). Contact your parallel programmer manufac- turer for more information on the parallel programmer. Refer to the user's manual included with your parallel programmer for instructions.
Page 288: Electrical Characteristics
23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics 23.1 Electrical Characteristics (M16C/62P) Table 23.1 Absolute Maximum Ratings S y m b o l P a r a m e t e r Condition R a t e d V a l u e...
Page 289 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) Table 23.2 Recommended Operating Conditions (1) Standard S y m b o l P a r a m e t e r U n i t Min. T y p . M a x .
Page 290 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) Table 23.3 A/D Conversion Characteristics Standard S y m b o l P a r a m e t e r Measuring Condition U n i t Min. T y p . M a x .
Page 291 10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (D7, D9, U7 and U9). 11. Customers desiring E/W failure rate information should contact their Renesas technical support representative. Table 23.7 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics...
Page 292 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) Table 23.8 Low Voltage Detection Circuit Electrical Characteristics S t a n d a r d S y m b o l M e a s u r i n g C o n d i t i o n...
Page 293 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Table 23.10 Electrical Characteristics S t a n d a r d Symbol M e a s u r i n g C o n d i t i o n...
Page 294 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Table 23.11 Electrical Characteristics (2) S t a n d a r d S y m b o l P a r a m e t e r Measuring Condition U n i t M i n .
Page 295 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 23.12 External Clock Input (XIN input)
Page 296 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 23.14 Timer A Input (Counter Input in Event Counter Mode)
Page 297 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 23.20 Timer B Input (Counter Input in Event Counter Mode)
Page 298 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Switching Characteristics = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 23.26 Memory Expansion and Microprocessor Modes (for setting with no wait)
Page 299 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Switching Characteristics = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 23.27 Memory Expansion and Microprocessor Modes...
Page 300 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Switching Characteristics = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 23.28 Memory Expansion and Microprocessor Modes...
Page 301 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling h(TIN–UP) su(UP–TIN)
Page 302 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TXDi d(C–Q) su(D–C) h(C–D) RXDi w(INL) INTi input w(INH) Figure 23.4 Timing Diagram (2) page 288...
Page 303 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Memory Expansion Mode, Microprocessor Mode (Common to setting with wait and setting without wait) BCLK HOLD input HLDA output P0, P1, P2, P3, P4, P5_0 to P5_2 Measuring conditions : •...
Page 304 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Memory Expansion Mode, Microprocessor Mode (For setting with no wait) Read timing BCLK d(BCLK-CS) h(BCLK-CS) 25ns.max 4ns.min d(BCLK-AD) h(BCLK-AD) 25ns.max 4ns.min d(BCLK-ALE) h(BCLK-ALE) h(RD-AD) -4ns.min 25ns.max 0ns.min d(BCLK-RD) h(BCLK-RD) 25ns.max 0ns.min...
Page 305 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Read timing BCLK d(BCLK-CS) h(BCLK-CS) 25ns.max 4ns.min d(BCLK-AD) h(BCLK-AD) 25ns.max 4ns.min h(BCLK-ALE) -4ns.min 25ns.max h(BCLK-RD) 25ns.max 0ns.min Hi-Z h(RD-DB) su(DB-RD) 0ns.min 40ns.min page 291...
Page 306 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Memory Expansion Mode, Microprocessor Mode for 2-wait setting and external area access Read timing BCLK h(BCLK-CS) d(BCLK-CS) 4ns.min 25ns.max h(BCLK-AD) d(BCLK-AD) 25ns.max 4ns.min d(BCLK-ALE) h(RD-AD) h(BCLK-ALE) 25ns.max 0ns.min -4ns.min h(BCLK-RD) d(BCLK-RD) 25ns.max...
Page 307 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Memory Expansion Mode, Microprocessor Mode for 3-wait setting and external area access Read timing BCLK Write timing BCLK WR, WRL Figure 23.9 Timing Diagram (7) page 293...
Page 308 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Memory Expansion Mode, Microprocessor Mode For 1- or 2-wait setting, external area access and multiplex bus selection Read timing BCLK h(BCLK-CS) d(BCLK-CS) h(RD-CS) 4ns.min tcyc (0.5 X tcyc-10)ns.min 25ns.max d(AD-ALE) (0.5 X tcyc-25)ns.min...
Page 309 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Memory Expansion Mode, Microprocessor Mode For 3-wait setting, external area access and multiplex bus selection Read timing BCLK h(RD-CS) h(BCLK-CS) (0.5 X tcyc-10)ns.min 4ns.min d(BCLK-CS) 25ns.max d(AD-ALE) h(ALE-AD) (0.5 X tcyc-25)ns.min (0.5 X tcyc-15)ns.min...
Page 310 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Table 23.29 Electrical Characteristics Standard M e a s u r i n g C o n d i t i o n S y m b o l P a r a m e t e r Unit M i n .
Page 311 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Table 23.30 Electrical Characteristics (2) S t a n d a r d S y m b o l Measuring Condition P a r a m e t e r U n i t M i n .
Page 312 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 23.31 External Clock Input (XIN Input)
Page 313 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 23.33 Timer A Input (Counter Input in Event Counter Mode)
Page 314 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 23.39 Timer B Input (Counter Input in Event Counter Mode)
Page 315 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Switching Characteristics = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 23.45 Memory Expansion, Microprocessor Modes (for setting with no wait)
Page 316 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Switching Characteristics Table 23.46 Memory expansion and Microprocessor Modes (for 1- to 3-wait setting and external area access) S t a n d a r d M e a s u r i n g...
Page 317 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Switching Characteristics = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C, unless otherwise specified) Table 23.47 Memory expansion and Microprocessor Modes...
Page 318 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During Event Counter Mode TAiIN input (When count on falling h(TIN–UP) su(UP–TIN)
Page 319 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TXDi su(D–C) d(C–Q) h(C–D) RXDi w(INL) INTi input w(INH) Figure 23.14 Timing Diagram (2) page 305...
Page 320 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Memory Expansion Mode, Microprocessor Mode (Effective for setting with wait) BCLK (Separate bus) WR, WRL, WRH (Separate bus) (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input su(RDY–BCLK) h(BCLK–RDY) (Common to setting with wait and setting without wait) BCLK su(HOLD–BCLK)
Page 321 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Memory Expansion Mode, Microprocessor Mode (for setting with no wait) Read timing BCLK d(BCLK-CS) h(BCLK-CS) 30ns.max 4ns.min d(BCLK-AD) h(BCLK-AD) 30ns.max 4ns.min d(BCLK-ALE) h(BCLK-ALE) h(RD-AD) -4ns.min 30ns.max 0ns.min d(BCLK-RD) h(BCLK-RD) 30ns.max 0ns.min...
Page 322 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Read timing BCLK d(BCLK-CS) h(BCLK-CS) 30ns.max 4ns.min d(BCLK-AD) h(BCLK-AD) 30ns.max 4ns.min h(BCLK-ALE) -4ns.min 30ns.max h(BCLK-RD) 30ns.max 0ns.min Hi-Z h(RD-DB) su(DB-RD) 0ns.min 50ns.min BCLK d(BCLK-CS) 30ns.max d(BCLK-AD) 30ns.max d(BCLK-AD) h(BCLK-WR) 30ns.max 0ns.min...
Page 323 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Memory Expansion Mode, Microprocessor Mode for 2-wait setting and external area access Read timing BCLK h(BCLK-CS) d(BCLK-CS) 4ns.min 30ns.max h(BCLK-AD) d(BCLK-AD) 4ns.min 30ns.max d(BCLK-ALE) h(RD-AD) h(BCLK-ALE) 30ns.max 0ns.min -4ns.min d(BCLK-RD) h(BCLK-RD) 30ns.max...
Page 324 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Memory Expansion Mode, Microprocessor Mode for 3-wait setting and external area access Read timing BCLK h(BCLK-CS) d(BCLK-CS) 4ns.min 30ns.max h(BCLK-AD) d(BCLK-AD) 4ns.min 30ns.max d(BCLK-ALE) h(RD-AD) h(BCLK-ALE) 30ns.max 0ns.min -4ns.min h(BCLK-RD) d(BCLK-RD) 0ns.min...
Page 325 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Memory Expansion Mode, Microprocessor Mode For 2-wait setting, external area access and multiplex bus selection Read timing BCLK h(BCLK-CS) d(BCLK-CS) h(RD-CS) 4ns.min (0.5 X tcyc-10)ns.min 40ns.max d(AD-ALE) (0.5 X tcyc-40)ns.min h(ALE-AD) (0.5 X tcyc-15)ns.min...
Page 326 23. Electrical Characteristics (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) = 3V Memory Expansion Mode, Microprocessor Mode For 3-wait setting, external area access and multiplex bus selection Read timing BCLK /DBi Write timing BCLK /DBi Figure 23.21 Timing Diagram (9) page 312...
Page 327: Electrical Characteristics (M16C/62Pt)
23. Electrical Characteristics (M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) 23.2 Electrical Characteristics (M16C/62PT) Table 23.48 Absolute Maximum Ratings S y m b o l P a r a m e t e r Condition Rated Value U n i t S u p p l y V o l t a g e = A V - 0 .
Page 328 23. Electrical Characteristics (M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) Table 23.49 Recommended Operating Conditions S t a n d a r d Symbol P a r a m e t e r Unit T y p . M a x .
Page 329 23. Electrical Characteristics (M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) Table 23.50 A/D Conversion Characteristics S t a n d a r d 65d011 Tw(CC1)Tj0 G0.2Vj-1 3 TD( )Tj1.336E51 1 6D(0)Tj-0.667 8.97630CC1 M i n . T y p . M a x .
Page 330 10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (B7 and U7). 11. Customers desiring E/W failure rate information should contact their Renesas technical support representative. Table 23.54 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics...
Page 331 23. Electrical Characteristics (M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) Table 23.55 Power Supply Circuit Timing Characteristics S t a n d a r d S y m b o l P a r a m e t e r M e a s u r i n g c o n d i t i o n Unit Min.
Page 332 23. Electrical Characteristics (M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Table 23.56 Electrical Characteristics Standard S y m b o l P a r a m e t e r M e a s u r i n g C o n d i t i o n U n i t Min.
Page 333 23. Electrical Characteristics (M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Table 23.57 Electrical Characteristics (2) S t a n d a r d S y m b o l M e a s u r i n g C o n d i t i o n...
Page 334 23. Electrical Characteristics (M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Timing Requirements = 5V, V = 0V, at T = – 40 to 85 C (T version) / – 40 to 125 C (V version) unless otherwise specified) Table 23.58 External Clock Input (XIN input)
Page 335 23. Electrical Characteristics (M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Timing Requirements = 5V, V = 0V, at T = – 40 to 85 C (T version) / – 40 to 125 C (V version) unless otherwise specified) Table 23.59 Timer A Input (Counter Input in Event Counter Mode)
Page 336 23. Electrical Characteristics (M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Timing Requirements = 5V, V = 0V, at T = – 40 to 85 C (T version) / – 40 to 125 C (V version) unless otherwise specified) Table 23.65 Timer B Input (Counter Input in Event Counter Mode)
Page 337 23. Electrical Characteristics (M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) = 5V Switching Characteristics = 5V, V = 0V, at T = – 40 to 85 C (T version) / – 40 to 125 C (V version) unless otherwise specified) 30pF Figure 23.23 Ports P0 to P10 Measurement Circuit...
Page 338 23. Electrical Characteristics (M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) = 5V XIN input w(L) w(H) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During Event Counter Mode TAiIN input h(TIN–UP) (When count on falling su(UP–TIN)
Page 339 23. Electrical Characteristics (M16C/62PT) M16C/62P Group (M16C/62P, M16C/62PT) = 5V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TXDi su(D–C) d(C–Q) h(C–D) RXDi w(INL) INTi input w(INH) Figure 23.25 Timing Diagram (2) page 325...
Page 340: Usage Precaution
24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24. Usage Precaution 24.1 Reset When supplying power to the microcomputer, the power supply voltage applied to the VCC1 pin must meet the conditions of SVCC. Standard Symbol Parameter Unit Min. Typ. Max.
Page 341: Bus
24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.2 Bus • The ROMless version can operate only in the microprocessor mode, connect the CNVSS pin to VCC1. • When resetting CNVss pin with “H” input, contents of internal ROM cannot be read out.
Page 342: Pll Frequency Synthesizer
24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.3 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met. S t a n d a r d S y m b o l P a r a m e t e r U n i t T y p .
Page 343: Power Control
24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.4 Power Control ____________ • When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is stabilized. • Set the MR0 bit in the TAiMR register (i=0 to 4) to “0” (pulse is not output) to use the timer A to exit stop mode.
Page 344: Protect
24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.5 Protect Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0” (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to “1”.
Page 345 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.6 Interrupts 24.6.1 Reading address 00000h Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 00000h during the interrupt sequence.
Page 346 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.6.4 Changing the Interrupt Generate Factor If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0”...
Page 347 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.6.6 Rewrite the Interrupt Control Register (a) The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
Page 348 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.6.7 Watchdog Timer Interrupt Initialize the watchdog timer after the watchdog timer interrupt occurs. page 334...
Page 349 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.7 DMAC 24.7.1 Write to DMAE Bit in DMiCON Register When both of the conditions below are met, follow the steps below. Conditions • The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).
Page 350 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.8 Timers 24.8.1 Timer A 24.8.1.1 Timer A (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count starts).
Page 351 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.8.1.2 Timer A (Event Counter Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
Page 352 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.8.1.3 Timer A (One-shot Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
Page 353 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.8.1.4 Timer A (Pulse Width Modulation Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
Page 354 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.8.2 Timer B 24.8.2.1 Timer B (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1”...
Page 355 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.8.2.2 Timer B (Event Counter Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1”...
Page 356 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.8.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5) register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Page 357 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.9 Serial I/O 24.9.1 Clock Synchronous Serial I/O 24.9.1.1 Transmission/reception _______ ________ With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmission side that the ________ reception has become ready.
Page 358 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.9.1.2 Transmission When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state;...
Page 359 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.9.1.3 Reception In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix settings for transmission even when using the device only for reception. Dummy data is output to the outside from the TXDi pin when receiving data.
Page 360 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.9.2 UART 24.9.2.1 Special Mode 1(I C Mode) When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register to “0” and wait for more than half cycle of the transfer clock before setting each condition generate bit (STAREQ,RSTAREQ and STPREQ) from “0”...
Page 361 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.9.3 SI/O3, SI/O4 The SOUTi default value which is set to the SOUTi pin by the SMi7 bit approximately 10ns may be output when changing the SMi3 bit from “0” (I/O port) to “1” (SOUTi output and CLK function) while the SMi2 bit in the SiC (i=3 and 4) to “0”...
Page 362 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.10 A/D Converter Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref con- nected), start A/D conversion after passing 1 µs or longer.
Page 363 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi register after completion of A/D conversion, an incorrect value may be stored in the ADi register.
Page 364 M16C/62P Group (M16C/62P, M16C/62PT)
Page 365 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.12 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc.
Page 366 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.13 Mask ROM When using the masked ROM version, write nothing to internal ROM area. page 352...
Page 367 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.14 Flash Memory Version 24.14.1 Functions to Inhibit Rewriting Flash Memory Rewrite ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. If wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial I/O mode.
Page 368 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.14.7 Lock Bit Program Command Write “xx77h” in the first bus cycle and write “xxD0h” to the uppermost address of a block (even address, however) in the second bus cycle, and the lock bit for the specified block is cleared to “0”. Make sure the address value specified in the first bus cycle is the same uppermost block address that is specified in the second bus cycle.
Page 369 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.14.12 Writing in the user ROM area EW0 Mode • If the power supply voltage drops while rewriting any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse- quently, the flash memory becomes unable to be rewritten thereafter.
Page 370 24. Usage Precaution M16C/62P Group (M16C/62P, M16C/62PT) 24.15 Noise Connect a bypass capacitor (approximately 0.1 µF) across the VCC1 and XSS pins, and VCC2 and VSS pins using the shortest and thicker possible wiring. Figure 24.5 shows the bypass capacitor connection.
Page 371 M16C/62P Group (M16C/62P, M16C/62PT) 25. Differences Depending on Manufacturing Period Tables 25.1 and 25.2 list the precautions are applicable or not applicable every chip version of M16C/62P flash and ROM external versions. Contact separately about the mask ROM version. Table 25.1 Technical Update Applicable Table of M16C/62P Flash and ROM External Versions (1)
Page 372 25. Differences Depending on Manufacturing Period M16C/62P Group (M16C/62P, M16C/62PT) Table 25.2 Technical Update Applicable Table of M16C/62P Flash and ROM External Versions (2) TECHNICAL Chip version Precaution UPDATE When supplying power to the microcomputer, the power supply voltage –...
Page 373 Appendix 1. Package Dimensions M16C/62P Group (M16C/62P, M16C/62PT) Appendix 1. Package Dimensions Recommended 128P6Q-A Plastic 128pin 14 20mm body LQFP EIAJ Package Code JEDEC Code Weight(g) Lead Material LQFP128-P-1420-0.50 – – Cu Alloy Recommended Mount Pad Dimension in Millimeters Symbol 0.05...
Page 374 Appendix 1. Package Dimensions M16C/62P Group (M16C/62P, M16C/62PT) 100P6Q-A Plastic 100pin 14 14mm body LQFP Weight(g) Lead Material EIAJ Package Code JEDEC Code – Cu Alloy LQFP100-P-1414-0.50 0.63 Dimension in Millimeters Symbol – – – – 0.13 0.18 0.28 0.105 0.125...
Page 375 Appendix 2. Differences Between M16C/62P and M16C/62A M16C/62P Group (M16C/62P, M16C/62PT) Appendix 2. Differences Between M16C/62P and M16C/62A Appendix Table 2.1 Differences in Mask ROM Version and Flash Memory Version (1) Item M16C/62P M16C/62A Shortest instruction 41.7ns (f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 62.5ns (f(XIN)=16MHz, VCC=4.2V to 5.5V)
Page 376 Appendix 2. Differences Between M16C/62P and M16C/62A M16C/62P Group (M16C/62P, M16C/62PT) Appendix Table 2.2 Differences in Mask ROM Version and Flash Memory Version (2) Item M16C/62P M16C/62A Timers A, B count Selectable: f1, f2, f8, f32, fC32 Selectable: f1, f8, f32, fC32...
Page 377 Appendix 2. Differences Between M16C/62P and M16C/62A M16C/62P Group (M16C/62P, M16C/62PT) Appendix Table 2.3 Differences in Flash Memory Version Item M16C/62P M16C/62A User ROM blocks 14 blocks: 4 Kbytes x 3, 8 Kbytes x 3, 7 blocks: 8 Kbytes x 2, 16 Kbytes x1,...
Page 378 Register Index M16C/62P Group (M16C/62P, M16C/62PT) Register Index IDB1 ........148 TA0MR to TA4MR ....123 IFSR ........103 TA1 .......... 149 IFSR2A ........103 TA11 ........149 AD0 to AD7 ......210 INT0IC to INT5IC ...... 95 TA1MR ........151 ADCON0 .........
Page 379 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual REVISION HISTORY Rev. Date Description Page Summary 1.0 Jan/31/Y03 Applications are partly revised. (Continued) Table 1.1.1 is partly revised. Table 1.1.3 is partly revised. Figure 1.1.2 is partly revised. Explanation of “Memory” is partly revised.
Page 380 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual REVISION HISTORY Rev. Date Description Page Summary 1.0 Jan/31/Y03 Figure 1.15.3 is partly revised. (Continued) Figure 1.15.7 is partly revised. Figure 1.15.8 is partly revised. Figure 1.16.1 is partly revised. Figure 1.16.3 is partly revised.
Page 381 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual REVISION HISTORY Rev. Date Description Page Summary 1.0 Jan/31/Y03 Measurement conditions of switching characteristics are partly revised. Figure 1.26.12 is partly revised. Figure 1.26.15 is partly revised. Figure 1.26.16 is partly revised. Figure 1.26.17 is partly revised.
Page 382 Explanation of “Address Match Interrupt” is partly revised. Figure 1. 11.12 is changed into Table 1.11.6. 93-94 Notes are deleted. (All notes are indicated in “M16C/62 GROUP (M16C/62P) USAGE NOTES”). Explanation of “Watchdog Timer” is partly revised. A formula is added.
Page 383 Figure 1.12.2 is revised. 2.30 Sep 01,2004 Since high reliability version is added, a group name is revised. M16C/62P Group (M16C/62P) M16C/62P Group (M16C/62P, M16C/62PT) Table 1.1 to 1.3 are revised. Note 3 is partly revised. Figure 1.2 Note5 is deleted.
Page 384 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual REVISION HISTORY Rev. Date Description Page Summary 2.30 Sep 01,2004 18, 20 Table 1.11 to 1.13 are revised. 19,21 Table 1.12 to 1.14 are revised. Figure 3.1 is partly revised. Note 3 is added.
Page 385 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual REVISION HISTORY Rev. Date Description Page Summary 2.30 Sep 01,2004 Note 3 in Table 17.5 is added. 17.1.2.1 Bit Rates is added. 17.1.2.2 Counter Measure for Communication Error Occurs is added. _______ _______ 17.1.2.6 CTS/RTS Function is added.
Page 386 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual REVISION HISTORY Rev. Date Description Page Summary 2.30 Sep 01,2004 307-308 Figure 23.16 to 23.17 is partly revised. 309-310 Figure 23.18 to 23.19 is partly revised. 313-339 23.2 Electrical Characteristics (M16C/62PT) is added. 24.1 Reset is added.
Page 387 RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL M16C/62P Group (M16C/62P, M16C/62PT) Publication Data : Rev.1.00 Jan 31, 2003 Rev.2.30 Sep 01, 2004 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 388 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...

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Renesas M16C/62P Hardware Manual

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