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M16C/5L Group, M16C/56 Group
23.1.20.3 EPIF Bit
The EPIF bit is set to 1 when the CAN error state becomes error-passive (the REC or TEC value
exceeds 127).
This bit is set to 1 only when the REC or TEC initially exceeds 127. Thus, if 0 is written by a program
while the REC or TEC remains greater than 127, this bit is not set to 1 until the REC and the TEC go
below 127 and then exceed 127 again.
23.1.20.4 BOEIF Bit
The BOEIF bit is set to 1 when the CAN error state becomes bus-off (the TEC value exceeds 255).
This bit is also set to 1 when the BOM bit in the C0CTLR register is 01b (entry to CAN halt mode
automatically at bus-off entry) and the CAN module becomes the bus-off state.
23.1.20.5 BORIF Bit
The BORIF bit is set to 1 when the CAN module recovers from the bus-off state normally by detecting
11 consecutive bits 128 times in the following conditions:
(1) When the BOM bit in the C0CTLR register is 00b.
(2) When the BOM bit is 10b.
(3) When the BOM bit is 11b.
The BORIF bit is not set to 1 if the CAN module recovers from the bus-off state in the following
conditions:
(1) When the CANM bit in the C0CTLR register is set to 01b (CAN reset mode).
(2) When the RBOC bit in the C0CTLR register is set to 1 (forcible return from bus-off).
(3) When the BOM bit is 01b.
(4) When the BOM bit is 11b and the CANM bit is set to 10b (CAN halt mode) before normal recovery
occurs.
Table 23.8 lists the behavior of bits BOEIF and BORIF according to BOM bit setting value.
Table 23.8
Behavior of Bits BOEIF and BORIF according to BOM Bit Setting Value
BOM Bit
00b
01b
Set to 1 on entry to the bus-off
10b
state.
11b
23.1.20.6 ORIF Bit
The ORIF bit is set to 1 when a receive overrun occurs.
This bit is not to set to 1 in overwrite mode. In overwrite mode, a reception complete interrupt request is
generated if an overwrite condition occurs and this bit is not set to 1.
In normal mailbox mode, if an overrun occurs in any of mailboxes [0] to [31] in overrun mode, this bit is
set to 1.
In FIFO mailbox mode, if an overrun occurs in any of mailboxes [0] to [23] or the receive FIFO in
overrun mode, this bit is set to 1.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
BOEIF Bit
Set to 1 on exit from the bus-off state.
Do not set to 1.
Set to 1 on exit from the bus-off state.
Set to 1 if normal bus-off recovery occurs before the
CANM bit is set to 10b (CAN halt mode).
23. CAN Module
BORIF Bit
Page 588 of 803
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