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M16C/5L Group, M16C/56 Group
24.7
Notes on A/D Converter
24.7.1
Analog Input Pin
Do not use any pin from AN4 to AN7 as analog input pin if any pin from KI0 to KI3 is used as a key input
interrupt.
24.7.2
Pin Configuration
To prevent operation errors due to noise or latchup, and to reduce conversion errors, place capacitors
between the AVSS pin and the AVCC pin, the VREF pin, and analog inputs (ANi (i = 0 to 7), AN0_i,
AN2_i, and AN3_0 to AN3_2). Also, place a capacitor between the VCC pin and VSS pin.
ANi: ANi (i = 0 to 7), AN0_i, AN2_i, and AN3_0 to AN3_2
Notes:
1. Reference values: C1 ≥ 0.47 μF, C2 ≥ 0.47 μF, C3 ≥ 100 pF, C4 ≥ 0.1 μF
2. The traces for the capacitor and MCU should be as short and as wide as much as physically
possible.
Figure 24.13 Example of Pin Configuration
24.7.3
Register Access
Set registers associated with A/D converter after setting the CKS3 bit in the ADCON2 register. However
the other bits in the ADCON2 register and the CKS3 bit can be set at the same time. After changing the
CKS3 bit, set the others in the same way.
Write registers ADCON0 (excluding the ADST bit), ADCON1, and ADCON2 when A/D conversion
stops (before a trigger is generated).
After A/D conversion stops, set the ADSTBY bit in the ADCON1 register from 1 to 0.
24.7.4
A/D Conversion Start
When rewriting the ADSTBY bit in the ADCON1 register from 0 (A/D operation stopped) to 1 (A/D
operation enabled), wait for one φ AD cycle or more before starting A/D conversion.
24.7.5
A/D Operation Mode Change
When the A/D operation mode has been changed, reselect analog input pins by using bits CH2 to CH0
in the ADCON0 register or bits SCAN1 to SCAN0 in the ADCON1 register.
24.7.6
State When Forcibly Terminated
If A/D conversion in progress is halted by setting the ADST bit in the ADCON0 register to 0 (A/D
conversion stopped), the conversion result is undefined. In addition, the unconverted ADi register
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
MCU
VCC
AVCC
VCC
C4
VREF
VSS
AVSS
ANi
VCC
C2
C1
C3
24. A/D Converter
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