Renesas M16C/50 Series User Manual page 407

M16C/5L Group, M16C/56 Group
18.3.1.1 Increment
The counter starts incrementing from 0000h to FFFFh, then returns back to 0000h, and continues to
increment.
Counter operation
When the IT bit in the G1BCR0 register
is 1 (IC/OC base timer interrupt
generated by the overflow of bit 14)
b14 of the base timer
IR bit in the BTIC register
When the IT bit in the G1BCR0 register
is 0 (IC/OC base timer interrupt
generated by the overflow of bit 15)
b15 of the base timer
IR bit in the BTIC register
The above assumes the following:
• The RST4 bit in the G1BCR0 register is 0 (base timer is not reset when the base timer and G1BTRR registers value match).
• The RST1 bit in the G1BCR1 register is 0 (base timer is not reset when the base timer and G1PO0 registers value match).
• Bits UD1 and UD0 in the G1BCR1 register are 00b (increment).
Figure 18.4 Increment
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
FFFFh
C000h
8000h
4000h
0000h
1
0
Set to 0 by an interrupt request or by a program
1
0
Set to 0 by an interrupt request or by a program
18. Timer S
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