Advertisement
M16C/5L Group, M16C/56 Group
21.2.7
UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 to 4)
UARTi Transmit/Receive Control Register 1 (i = 0 to 4)
b7 b6 b5 b4
b3
b2
b1
UiLCH (Data logic select bit) (b6)
The UiLCH bit is enabled when bits SMD2 to SMD0 in the UiMR register are 001b (clock synchronous
serial I/O mode), 100b (UART mode, 7-bit character), or 101b (UART mode, 8-bit character). Set this bit
to 0 when bits SMD2 to SMD0 are set to 010b (I
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
b0
U0C1, U1C1, U2C1
U4C1, U3C1
Bit symbol
Bit Name
TE
Transmit enable bit
TI
Transmit buffer empty flag
RE
Receive enable bit
RI
Receive complete flag
UARTi transmit interrupt
UilRS
source select bit
UARTi continuous receive
UiRRM
mode enable bit
UiLCH
Data logic select bit
UiERE
Error signal output enable bit
21. Serial Interface UARTi (i = 0 to 4)
Address
024Dh, 025Dh, 026Dh
029Dh, 02ADh
Function
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in UiTB register
1 : No data present in UiTB register
0 : Reception disabled
1 : Reception enabled
0 : No data present in UiRB register
1 : Data present in UiRB register
0 : UiTB register empty (TI = 1)
1 : Transmission completed (TXEPT = 1)
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
0 : Not inverted
1 : Inverted
0 : Output disabled
1 : Output enabled
2
C mode) or 110b (UART mode, 9-bit character).
Reset Value
0000 0010b
0000 0010b
RW
RW
RO
RW
RO
RW
RW
RW
RW
Page 441 of 803
Advertisement
