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M16C/5L Group, M16C/56 Group
Timing Requirements
(V
= 3 V, V
= 0 V, at T
CC
SS
27.3.2.5
Timer S Input
Table 27.41
Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode)
Symbol
t
TSUDA, TSUDB input high pulse width
w(TSH)
t
TSUDA, TSUDB input low pulse width
w(TSL)
t
TSUDB input setup time
su(TSUDA-TSUDB)
t
TSUDA input setup time
su(TSUDB-TSUDA)
Two-phase pulse input in two-phase pulse signal processing mode
TSUDA input
TSUDB input
Note:
1.
When the TSUDA and TSUDB phases are interchanged, t
are also interchanged.
Figure 27.20 Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode)
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
= − 40 ° C to 85 ° C unless otherwise specified)
opr
Parameter
t w(TSH)
t su(TSUDA-TSUDB)
Min.
t w(TSL)
t su(TSUDA-TSUDB)
t w(TSH)
t su(TSUDB-TSUDA)
t su(TSUDB-TSUDA)
su(TSUDA-TSUDB)
27. Electrical Characteristics
J-Version, V
= 3 V
CC
Standard
Unit
Max.
μ s
2
μ s
2
μ s
1
μ s
1
t w(TSL)
and t
su(TSUDB-TSUDA)
Page 727 of 803
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