Renesas M16C/50 Series User Manual page 265

M16C/5L Group, M16C/56 Group
14.4 Interrupts
Refer to operation examples for interrupt request generation timing.
For details on interrupt control, refer to 12.7 "Interrupt Control".
Table 14.10 DMAC Interrupt Related Registers
Address
004Bh DMA0 Interrupt Control Register
004Ch DMA1 Interrupt Control Register
0069h DMA2 Interrupt Control Register
006Ah DMA3 Interrupt Control Register
When the DMS bit or bits DSEL4 to DSEL0 in the DMiSL register are changed, the DMAS bit in the
DMiCON sometimes becomes 1 (DMA requested) (i = 0 to 3). Therefore, set the DMAS bit to 0 (DMA not
requested) after the DMS bit or bits DSEL4 to DSEL0 in the DMiSL register are changed. Refer to 12.13
"Notes on Interrupts" for more details.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Register Symbol Reset Value
DM0IC XXXX X000b
DM1IC XXXX X000b
DM2IC XXXX X000b
DM3IC XXXX X000b
14. DMAC
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