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M16C/5L Group, M16C/56 Group
23.1.3
CAN0 Bit Configuration Register (C0BCR)
CAN0 Bit Configuration Register
b23
b16b15
b8
b7
0
Notes:
1. Set the C0BCR register before entering CAN halt mode from CAN reset mode or CAN operation mode from
CAN reset mode. After the setting is made once, this register can be written to in CAN reset mode or CAN
halt mode.
2. The C0BCR register consists of 24 bits. A 32-bit read/write access should be performed carefully not to
rewrite the C0CLKR register.
Figure 23.4
C0BCR Register
Refer to 23.3 "CAN Communication Speed Configuration" about the bit timing configuration.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
(1, 2)
b0
Symbol
C0BCR
Bit Symbol
Prescaler Division Ratio
BRP
Set Bit (10 bits)
—
Reserved
(b10)
—
No register bit; If necessary, set to 0. The read value is 0.
(b11)
TSEG1
Time Segment 1 Control Bit
TSEG2
Time Segment 2 Control Bit
—
No register bit; If necessary, set to 0. The read value is 0.
(b19)
Resynchronization Jump
SJW
Width Control Bit
—
No register bits; If necessary, set to 0. The read value is 0.
(b23-22)
Address
D7C6h-D7C4h
Bit Name
If the setting value is P (0 to 1023),
the baud rate prescaler divides fCAN
by P + 1
Set to 0.
b15b14b13b12
0 0 0 0 : Do not use this combination
0 0 0 1 : Do not use this combination
0 0 1 0 : Do not use this combination
0 0 1 1 : 4 Tq
0 1 0 0 : 5 Tq
0 1 0 1 : 6 Tq
0 1 1 0 : 7 Tq
0 1 1 1 : 8 Tq
1 0 0 0 : 9 Tq
1 0 0 1 : 10 Tq
1 0 1 0 : 11 Tq
1 0 1 1 : 12 Tq
1 1 0 0 : 13 Tq
1 1 0 1 : 14 Tq
1 1 1 0 : 15 Tq
1 1 1 1 : 16 Tq
b18b17b16
0 0 0 : Do not use this combination
0 0 1 : 2 Tq
0 1 0 : 3 Tq
0 1 1 : 4 Tq
1 0 0 : 5 Tq
1 0 1 : 6 Tq
1 1 0 : 7 Tq
1 1 1 : 8 Tq
b21b20
0 0 : 1 Tq
0 1 : 2 Tq
1 0 : 3 Tq
1 1 : 4 Tq
23. CAN Module
Reset Value
00 0000h
Function
RW
RW
RW
—
RW
RW
—
RW
—
Page 555 of 803
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