Advertisement
M16C/5L Group, M16C/56 Group
18.3.3.3
Set/Reset Waveform Output Mode (SR Waveform Output Mode)
The OUTC1_j pin outputs high when the INV bit in the G1POCRj register (j = 0, 2, 4, 6) is 0 (output level
is not inverted) and the base timer value matches the G1POj register value. When the base timer value
matches the G1POk register value (k = j + 1), the OUTC1_j pin outputs low.
When bits MOD1 and MOD0 in registers G1POCRj and G1POCRk are 01b (SR waveform output
mode), set bits UD1 and UD0 in the G1BCR register to 00b (increment).
Table 18.16 lists the specifications of SR waveform output mode and Figure 18.18 shows the
operational example of SR waveform output mode.
Table 18.16
SR Waveform Output Mode Specifications
Item
Output waveform
Waveform output start
condition
Waveform output stop
condition
Interrupt request
occurrence timing
OUTC1_ j pin
Selectable functions
j = 0, 2, 4, 6; k = j + 1
Note:
1.
When the RST1 bit in the G1BCR1 register is 1 (the base timer is reset by the G1PO0 register), SR waveform
output mode is disabled for channels 0 and 1.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
•
Free-running operation (when bits RST2 and RST1 in the G1BCR1 register and the RST4
bit in the G1BCR0 register are all 0 (the base timer is not reset))
65536
Cycle:
--------------- -
fBT1
Inverted output level width:
•
When the base timer matches either of following registers, the base timer is reset to 0000h:
•
G1PO0 register (when the RST1 bit is 1, and bits RST4 and RST2 are 0)
•
G1BTRR register (when the RST4 bit is 1, and bits RST2 and RST1 are 0)
p
Cycle:
------------ -
fBT1
Inverted output level width:
m: G1POj register setting value
n: G1POk register setting value
p: G1PO0 register or G1BTRR register value
0000h ≤ m < n < p ≤ FFFDh
Set bits IFEj and IFEk in the G1FE register to 1 (channel j function enabled).
Set bits IFEj and IFEk to 0 (channel j function disabled).
•
Channel j
When the base timer value matches the G1POj register value.
•
Channel k
When the base timer value matches the G1POk register value.
Pulse output or I/O port
•
Default value setting
Select the starting waveform output level.
•
Output level inversion
Select if the waveform level output from the OUTC1_j pin is inverted.
•
Output disabled
When the EOCj bit in the G1OER register is 1 (output disabled), the OUTC1_j pin stops
waveform output and becomes a programmable I/O port. When the EOCj bit is 0 (output
enabled), the OUTC1_j pin outputs SR waveform again.
Specification
n m
–
------------- -
fBT1
+
2
n m
–
------------- -
fBT1
18. Timer S
(1)
Page 389 of 803
Advertisement
