Renesas M16C/50 Series User Manual page 389

M16C/5L Group, M16C/56 Group
18.2.3 Waveform Generation Control Register j (G1POCRj) (j = 0 to 7)
Waveform Generation Control Register j
b7 b6 b5 b4 b3 b2 b1
0
Rewrite the G1POCRj register when the BTS bit in the G1BCR1 is 0 (base timer reset), the FSCj bit in
the G1FS register is 0 (waveform generation function selected), and the IFEj bit in the G1FE register is
0 (channel j function disabled). When the G1POCRj register is rewritten, set the BTS bit to 1 after one
or more fBT1 cycles.
MOD1 and MOD0 (Operating mode select bit) (b1-b0)
To select SR waveform output mode, set bits MOD1 and MOD0 of an even channel (channel j (j = 0, 2,
4, or 6)) and bits MOD1 and MOD0 of the next odd channel (channel j + 1) both to 01b. The waveform
is output from the OUT1_j pin of an even channel. In SR waveform output mode, set EOCj + 1 bit in the
G1OER register to 1 (output disabled).
IVL (Output default select bit) (b4)
When a value is written to the IVL bit, the FSCj bit (j = 0 to 7) in the G1FS register is set to 0 (waveform
generation function selected), and the IFEj bit in the G1FE register is set to 1 (channel j function
enabled), the set level is output.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
b0
Symbol
G1POCR0 to G1POCR3
G1POCR4 to G1POCR7
Bit Symbol Bit Name
MOD0
Operating mode select bit
MOD1
—
No register bits. If necessary, set to 0. The read value is undefined.
(b3-b2)
IVL Default output value select bit
G1POj register value reload
RLD
timing select bit
—
Reserved
(b6)
INV Output level inversion select bit
(j = 0 to 7)
Address
02D0h, 02D1h, 02D2h, 02D3h
02D4h, 02D5h, 02D6h, 02D7h
Function
b1 b0
0 0: Single waveform output mode
0 1: SR waveform output mode
1 0: Inverted waveform output mode
1 1: Do not set.
0: Output low as default value
1: Output high as default value
0: Reload the G1POj register on a write access
1: Reload the G1POj register when the base
timer is reset
Set to 0.
0: Output level not inverted
1: Output level inverted
18. Timer S
Reset Value
0X00 XX00b
0X00 XX00b
RW
RW
RW
—
RW
RW
RW
RW
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