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M16C/5L Group, M16C/56 Group
21.3.3.1
Detecting Start and Stop Conditions
Start and stop conditions are detected by their respective detectors.
Whether a start or a stop condition has been detected is determined.
A start condition detect interrupt request is generated when the SDA2 pin changes state from high to
low while the SCL2 pin is in the high state. A stop condition detect interrupt request is generated when
the SDA2 pin changes state from low to high while the SCL2 pin is in the high state.
Because the start and stop condition detect interrupts share the interrupt control register and vector,
check the BBS bit in the U2SMR register to determine which interrupt source is requesting the interrupt.
To detect a start or stop condition, both the set-up and hold times require at least six cycles of the
BRG2 count source as shown in Figure 21.16. To meet the condition for the Fast-mode specification,
the BRG2count source must be at least 10 MHz.
SDA2
SCL2
Start condition
Note:
1.
Figure 21.16 Detecting Start and Stop Conditions
21.3.3.2
Generating Start and Stop Conditions
A start condition is generated by setting the STAREQ bit in the U2SMR4 register to 1 (start).
A restart condition is generated by setting the RSTAREQ bit in the U2SMR4 register to 1 (start).
A stop condition is generated by setting the STPREQ bit in the U2SMR4 register to 1 (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to 1 (start).
(2) Set the STSPSEL bit in the U2SMR4 register to 1 (output).
The functions of the STSPSEL bit are shown in Table 21.17 and Figure 21.17.
Table 21.17
STSPSEL Bit Functions
Function
Output of pins SCL2 and
SDA2
Start/stop condition
Interrupt request
generation timing
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Hold time ≥
(1)
6 cycles
The number of cycles are the BRG2 count source cycles.
STSPSEL = 0
Output of transmit/receive clock and
data
Output of start/stop condition is
accomplished by a program using
ports (not automatically generated in
hardware)
Detection of start/stop condition
21. Serial Interface UARTi (i = 0 to 4)
Set-up time ≥
(1)
6 cycles
Stop condition
STSPSEL = 1
Output of a start/stop condition
according to bits STAREQ,
RSTAREQ, and STPREQ
Completion of generating start/stop
condition
Page 473 of 803
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