Advertisement
M16C/5L Group, M16C/56 Group
1.2
Specifications
Table 1.1 to Table 1.4 list specifications of the M16C/5L Group, M16C/56 Group.
Table 1.1
Specifications (80-pin Package) (1/2)
Item
CPU
Central processing unit
Memory
ROM, RAM, data flash
Voltage
Voltage detector
Detection
Clock
Clock generator
Programmable I/O
I/O Ports
ports
Interrupts
Watchdog Timer
DMA
DMAC
Timer A
Timer B
Timers
Timer function for three-
phase motor control
Timer S (Input
capture/output
compare)
Task monitoring timer
Real-time clock
Serial
UART0 to UART4
Interface
2
Multi-master I
C-bus Interface
A/D Converter
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Function
M16C/60 Series CPU Core (Multiplier: 16 × 16
unit: 16 × 16 + 32
•
Basic instructions: 91
•
Minimum instruction execution time:
31.25 ns (f(BCLK) = 32 MHz, VCC = 3.0 to 5.5 V)
•
Operating mode: Single-chip mode
See Table 1.5 and Table 1.6.
•
2 voltage detect points
•
5 circuits (Main clock, sub clock, PLL frequency synthesizer, 125 kHz on-
chip oscillator, 40 MHz on-chip oscillator)
•
Oscillation stop detector: Main clock oscillator stop/restart detection
•
Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable
•
Low-power consumption modes: Wait mode, stop mode
•
Real-time clock
•
71 CMOS inputs/outputs, a pull-up resistor selectable
•
Interrupt vectors: 70
External interrupt inputs: 11 (NMI, INT × 6, key input × 4)
•
•
Interrupt priority levels: 7
•
15 bits × 1 (with prescaler)
•
Automatic reset start function selectable
•
Dedicated 125 kHz on-chip oscillator for the watchdog timer contained
•
4 channels, Cycle-steal transfer mode
•
Trigger sources: 41
•
Transfer modes: 2 (single transfer, repeat transfer)
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (two-phase
encoder input) × 3
Programmable output mode × 3
16-bit timer × 3
Timer mode, event counter mode, pulse frequency measurement mode,
pulse-width measurement mode
Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
On-chip dead time timer
•
16-bit timer × 1 (base timer)
•
I/O: 8 channels
16-bit timer × 1 channel
Count: seconds, minutes, hours, weeks
4 channels (UART, clock synchronous serial interface)
1 channels (UART, clock synchronous serial interface, I
1 channel
10-bit resolution × 27 channels
Specification
32 bits))
1. Overview
32 bits, Multiply-accumulate
2
C-bus, IEBus)
Page 2 of 803
Advertisement
