Renesas M16C/50 Series User Manual page 491

M16C/5L Group, M16C/56 Group
21.3.1.1 CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i = 0 to 4) to select the transmit/receive clock polarity. Figure
21.4 shows the Transmit/Receive Clock Polarity.
(1) CKPOL bit in the UiC0 register is 0 (transmit data is output at the falling edge and the
receive data is input at the rising edge of the transmit/receive clock)
CLKi
TXDi
RXDi
(2) CKPOL bit is 1 (transmit data is output at the rising edge and the receive data is input at
the falling edge of the transmit/receive clock)
CLKi
TXDi
RXDi
i = 0 to 4
The above assumes the following:
• The CKDIR bit in the UiMR register is 0 (internal clock).
• The UFORM bit in the UiC0 register is 0 (LSB first).
• The UiLCH bit in the UiC1 register is 0 (not inverted).
Figure 21.4 Transmit/Receive Clock Polarity
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
21. Serial Interface UARTi (i = 0 to 4)
A high-level signal is output from the CLKi
pin while no data transmitted/received.
D4 D5 D6 D7
D4 D5 D6 D7
A low-level signal is output from the CLKi
pin while no data transmitted/received.
D4 D5 D6 D7
D4 D5 D6 D7
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