Advertisement
M16C/5L Group, M16C/56 Group
14.3.3
Transfer Cycles
A transfer cycle is composed of a bus cycle to read data from a source address (source read), and a
bus cycle to write data to a destination address (destination write). The number of read and write bus
cycles varies with the source and destination addresses.
Figure 14.2 shows Source Read Cycle Example. For convenience, the destination write cycle is shown
as one bus cycle and the source read cycles for the different conditions are shown. In reality, the
destination write cycle is subject to the same conditions as the source read cycle, with the transfer
cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for
the source read and the destination write cycle. For example, when data is transferred in 16-bit units,
and the source and destination addresses are both odd addresses ((2) in Figure 14.2), two source read
bus cycles and two destination write bus cycles are required.
14.3.3.1
Effect of Source and Destination Addresses
When a 16-bit unit of data is transferred and the source address starts with an odd address, the
source read cycle increments by one bus cycle, compared to a source address starting with an even
address.
When a 16-bit unit of data is transferred and the destination address starts with an odd address, the
destination write cycle increments by one bus cycle, compared to a destination address starting with
an even address.
14.3.3.2
Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of
bus cycles required increases by an amount equal to the number of software wait states.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
14. DMAC
Page 222 of 803
Advertisement
