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M16C/5L Group, M16C/56 Group
20.3
Operations
20.3.1
Basic Operation
The real-time clock generates a 1-second signal from the count source selected in the RTCCSR
register and counts seconds, minutes, hours, a.m./p.m., a day, and a week.
The day and time to start the count can be set using registers RTCSEC, RTCMIN, RTCHR, RTCWK,
and the RTCPM bit in the RTCCR1 register. Current time and day are read from registers RTCSEC,
RTCMIN, RTCHR, RTCWK, and the RTCPM bit in the RTCCR1 register. However, do not read these
registers when the BSY bit in the RTCSEC register is 1 (while data is updated).
An interrupt request can be generated every second, minute, hour, day, or week. While bits RTCCMP1
to RTCCMP0 in the RTCCR2 register are 00b (no compare mode), use the RTCCR2 register to enable
one of the periodic interrupts triggered every second, minute, hour, day and week. When a periodic
interrupt is generated, the IR bit in the RTCTIC register becomes 1 (interrupt request).
Figure 20.3 shows Real-Time Clock Basic Operating Example, Figure 20.4 shows Time and Day
Change Procedure (No Compare Mode or Compare Mode 1), and Figure 20.5 shows Time and Day
Change Procedure (Compare Mode 2 or Compare Mode 3).
Bits SC12 to SC00
in the RTCSEC register
Bits MN12 to MN00
in the RTCMIN register
Bits HR11 to HR00
in the RTCHR register
in the RTCCR1 register
Bits WK2 to WK0
in the RTCWK register
IR bit in the RTCTIC register
(when the SEIE bit in the RTCCR2
register is 1 (enable periodic
interrupt triggered every second))
IR bit in the RTCTIC register
(when the MNIE bit in the RTCCR2
register is 1 (enable periodic
interrupt triggered every minute))
BSY : Bit in RTCSEC register
Figure 20.3
Real-Time Clock Basic Operating Example
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
BSY bit
58
(Not changed)
RTCPM Bit
(Not changed)
(Not changed)
Approx.
62.5 ms
Undefined
59
03
This bit becomes 0 when an interrupt request
is accepted, or by setting the bit to 0.
20. Real-Time Clock
1s
Approx.
62.5 ms
Undefined
Undefined
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