Renesas M16C/50 Series User Manual page 610

M16C/5L Group, M16C/56 Group
23.1.11 CAN0 Receive FIFO Pointer Control Register (C0RFPCR)
CAN0 Receive FIFO Pointer Control Register
b7
Figure 23.13 C0RFPCR Register
When the receive FIFO is not empty, write FFh to the C0RFPCR register by a program to increment the
CPU-side pointer for the receive FIFO to the next mailbox location.
Do not write to the C0RFPCR register when the RFE bit in the C0RFCR register is 0 (receive FIFO
disabled).
Both the CAN-side pointer and the CPU-side pointer are incremented when a new message is received
and the RFFST bit is 1 (receive FIFO is full) in overwrite mode. When the RFMLF bit is 1 in this
condition, the CPU-side pointer cannot be incremented by writing to the C0RFPCR register by a
program.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
b0
Symbol
C0RFPCR
The CPU-side pointer for the receive FIFO is incremented by
writing FFh
Address
D7C9h
Function
23. CAN Module
Reset Value
Undefined
Setting Value RW
FFh
WO
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