Page 1 REJ09B0101-0100Z M16C/29 Group Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES Before using this material, please visit our website to confirm that this is the most current document available. Rev. 1.00 Revision date: Nov. 1, 2004 www.renesas.com...
Page 2 • The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
Page 3 How to Use This Manual This hardware manual provides detailed information on features in the M16C/29 Group microcomputer. Users are expected to have basic knowledge of electric circuits, logical circuits and micro- computer. Each register diagram contains bit functions with the following symbols and descriptions. XXX register Symbol Address...
Page 4 M16C Family Documents Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware specifications (pin assignments, Hardware Manual memory maps, specifications of peripheral func- tions, electrical characteristics, timing charts) Detailed description about instructions and mi- Software Manual crocomputer performance by each instruction •...
Page 5 Table of Contents Quick Reference to Pages Classified by Address ..............B-1 1. Overview ......................1 1.1 Applications ........................1 1.2 Performance Outline ......................2 1.3 Block Diagram ........................4 1.4 Product List ........................6 1.5 Pin Configuration ......................10 1.6 Pin Description .......................
Page 6: Table Of Contents
5.2 Software Reset ....................... 29 5.3 Watchdog Timer Reset ....................29 5.4 Oscillation Stop Detection Reset ..................29 5.5 Voltage Detection Circuit ....................31 5.5.1 Voltage Down Detection Interrupt ................34 5.5.2 Limitations on Exiting Stop Mode ................36 5.5.3 Limitations on Exiting Wait Mode ................36 6.
Page 7 7.8.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset)......58 7.8.2 Operation When CM27 bit = 1 (Oscillation Stop and Re-oscillation Detect Interrupt) ..58 7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function ......59 8. Protection .......................60 9.
Page 8 9.8 Key Input Interrupt ......................77 9.9 CAN0 Wake-up Interrupt ....................77 9.10 Address Match Interrupt ....................78 10. Watchdog Timer ...................80 10.1 Count source protective mode ..................80 10.2 Cold start / Warm start ....................82 11. DMAC ......................83 11.1 Transfer Cycles ......................
Page 9 13.1 Base Timer ......................... 144 13.1.1 Base Timer Reset Register .................. 148 13.2 Interrupt Operation ..................... 149 13.3 DMA Support ......................149 13.4 Time Measurement Function ..................150 13.5 Waveform Generation Function .................. 154 13.5.1 Single-Phase Waveform Output Mode ..............155 13.5.2 Phase-Delayed Waveform Output Mode..............
Page 10 14.1.4.1.2 Slave (External Clock) ................200 14.1.5 Special Mode 3 (IEBus mode)(UART2) .............. 202 14.1.6 Special Mode 4 (SIM Mode) (UART2)..............204 14.1.6.1 Parity Error Signal Output ................207 14.1.6.2 Format ......................208 14.2 SI/O3 and SI/O4 ......................209 14.2.1 SI/Oi Operation Timing ..................212 14.2.2 CLK Polarity Selection ..................
Page 11 16.4.5 Bit 7: I C bus interface pin input level select bit (TISS) ........260 16.5 I C0 Status Register (S10 register) ................261 16.5.1 Bit 0: Last receive bit (LRB) ................261 16.5.2 Bit 1: General call detection flag (ADR0) ............261 16.5.3 Bit 2: Slave address comparison flag (AAS) ............
Page 12 17.1.1. CAN0 Message Box .................... 282 17.1.2. Acceptance Mask Registers ................284 17.1.3. CAN SFR Registers .................... 285 17.1.3.1. C0MCTLj Register (j = 0 to 15) ..............285 17.1.3.2. C0CTLR Register ..................286 17.1.3.3. C0STR Register .................... 287 17.1.3.4. C0SSTR Register ..................288 17.1.3.5.
Page 13 19.2 Port Pi Register (Pi Register, i = 0 to 3, 6 to 10) ............309 19.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers) ..309 19.4 Port Control Register ....................309 19.5 Pin Assignment Control register (PACR) ..............310 19.6 Digital Debounce function ...................
Page 14 21.6.4 How to Access ...................... 380 21.6.5 Writing in the User ROM Space ................380 21.6.5.1 EW0 Mode ..................... 380 21.6.5.2 EW1 Mode ..................... 380 21.6.6 DMA Transfer ....................... 381 21.6.7 Writing Command and Data ................. 381 21.6.8 Wait Mode ......................381 21.6.9 Stop Mode ......................
Page 15 Quick Reference to Pages Classified by Address Register Symbol Page Register Symbol Page Address Address 0000 0040 CAN0 wakeup interrupt control register C01WKIC 0001 0041 C0RECIC 0002 0042 CAN0 successful reception interrupt control register C0TRMIC 0003 0043 CAN0 successful transmission interrupt control regiser Processor mode register 0 INT3 interrupt control register INT3IC...
Page 16 Quick Reference to Pages Classified by Address Register Symbol Page Register Symbol Page Address Address 00C0 0080 0081 00C1 0082 00C2 CAN0 message box 2: Identifier/DLC CAN0 message box 6: Identifier/DLC 00C3 0083 0084 00C4 0085 00C5 00C6 0086 0087 00C7 0088 00C8...
Page 17 Quick Reference to Pages Classified by Address Register Symbol Page Register Symbol Page Address Address 0140 0100 0101 0141 0102 0142 CAN0 message box 10: Identifer/DLC CAN0 message box 14: Identifier/DLC 0103 0143 0104 0144 0105 0145 0106 0146 0107 0147 0108 0148...
Page 18 Quick Reference to Pages Classified by Address Register Symbol Page Register Symbol Page Address Address 0180 0240 0181 0241 0242 0182 CAN0 acceptance filter support register C0AFS 0183 0243 0184 0244 0245 0185 0186 0246 0247 0248 0249 01B0 024A 024C 01B1 01B2...
Page 19 Quick Reference to Pages Classified by Address Register Symbol Page Register Symbol Page Address Address 0300 0340 TM, WG register 0 139, 140 G1TM0, G1PO0 0301 0341 0342 0302 TM, WG register 1 Timer A1-1 register TA11 139, 140 G1TM1, G1PO1 0343 0303 0344...
Page 20 Quick Reference to Pages Classified by Address Register Symbol Page Register Symbol Page Address Address 99, 110, 03C0 0380 Count start flag TABSR A/D register 0 03C1 Clock prescaler reset flag CPSRF 97, 110 0381 03C2 A/D register 1 One-shot start flag ONSF 0382 03C3...
Page 21 M16C/29 Group REJ09B0101-0100Z SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.00 Nov 01,2004 1. Overview The M16C/29 group of single-chip microcomputers is built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and is packaged in a 64-pin and 80-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc- tion efficiency.
Page 22 M16C/29 Group 1. Overview 1.2 Performance Outline Table 1.2.1 lists performance outline of M16C/29 group 80-pin device. Table 1.2.2 lists performance outline of M16C/29 group 64-pin device. Table 1.2.1. Performance outline of M16C/29 group (80-pin device) Item Performance Number of basic instructions 91 instructions Shortest instruction 50 ns (f(BCLK)= 20MH = 3.0V to 5.5V)
Page 23 M16C/29 Group 1. Overview Table 1.2.2. Performance outline of M16C/29 group (64-pin device) Item Performance Number of basic instructions 91 instructions Shortest instruction 50 ns (f(BCLK)= 20MH = 3.0V to 5.5V) (Normal-ver./T-ver.) excution time 100 ns (f(BCLK)= 10MH = 2.7V to 5.5V) (Normal-ver.) 50 ns (f(BCLK)= 20MH = 4.2V to 5.5V -40 to 105°C)
Page 24 M16C/29 Group 1. Overview 1.3 Block Diagram Figure 1.3.1 is a block diagram of the M16C/29 group, 80-pin device. Port P0 Port P1 Port P2 Port P3 Port P6 Port P7 Port P8 Port P9 Port P10 Ports Internal Peripheral Functions Timer Timer S Serial Ports...
Page 25 M16C/29 Group 1. Overview Figure 1.3.2 is a block diagram of the M16C/29 group, 64-pin device. Port P0 Port P1 Port P2 Port P3 Port P6 Port P7 Port P8 Port P9 Port P10 Ports Internal Peripheral Functions Timer Timer S Serial Ports System Clock Generator Timer A0 (16 bits)
Page 26 M16C/29 Group 1. Overview 1.4 Product List Tables 1.4.1 to 1.4.3 list the M16C/29 group products and Figure 1.4.1 shows the type numbers, memory sizes and packages. Tables 1.4.4 to 1.4.6 list the product code of flash memory version for M16C/29 group. Figure 1.4.2 shows the marking diagram of flash memory version for M16C/29 group Normal-ver.Figure 1.4.3 shows the marking diagram of flash memory version for M16C/29 group T-ver.Figure 1.4.4 shows the marking diagram of flash memory version for M16C/29 group V-ver.
Page 27 M16C/29 Group 1. Overview Table 1.4.3. Product List (3) -V Version As of September 2004 Type No. ROM capacity RAM capacity Package type Remarks M30290F8VHP 64K + 4K byte 4K byte M30290FAVHP 96K + 4K byte 8K byte 80P6Q-A Flash ROM Version M30290FCVHP 128K + 4K byte 12K byte...
Page 28 M16C/29 Group 1. Overview Table 1.4.4 Product Code of Flash Memory version -M16C/29 group Normal-ver. Internal ROM(Program Area) Internal ROM(Data Area) Operating Product Program Program Package Temperature Temperature Ambient Code and Erase and Erase Temperature Range Range Endurance Endurance -40°C to 85°C 0°...
Page 29 M16C/29 Group 1. Overview (1) Flash ROM Version, 80P6Q-A, T-ver. M16C Product Name : indicates M30290FATHP M30290FATHP Chip Version and Product Code: A U3 A : indicates chip version XXXXXXX The first edition is shown to be blank and continues with A and B. U3 : indicates product code (see Table 1.4.5) Date Code (7 digits) : indicates manufacturing management code (2) Flash ROM Version, 64P6Q-A, T-ver.
Page 30 M16C/29 Group 1. Overview 1.5 Pin Configuration Figures 1.5.1 and 1.5.2 show the pin configurations (top view). PIN CONFIGURATION (top view)(Note) Note. Set PACR2 to PACR0 bit in the PACR register Package: 80P6Q-A to "011b" before you input and output it after resetting to each pin.
Page 31 M16C/29 Group 1. Overview PIN CONFIGURATION (top view)(Note) Note. Set PACR2 to PACR0 bit in the PACR register to "010b" before you input and output it afer resetting to each pin. When the PACR register isn’t set up, the input and output function of some of the pins are disabled.
Page 32 M16C/29 Group 1. Overview 1.6 Pin Description Table 1.6.1 and 1.6.2 describes the available pins. Table 1.6.1 Pin Description(1) Pin Name Signal name I/O type Function Power supply Apply 0V to the Vss pin, and the following voltage to the Vcc pin. input 2.7 to 5.5V (Normal-ver.) 3.0 to 5.5V (T-ver.)
Page 33 M16C/29 Group 1. Overview Table 1.6.2 Pin Description(2) Pin Name Signal name I/O type Function I/O port P7 Input/Output This is an 8-bit I/O port equivalent to P0. P7 can also function as I/O for timer A0 to A3, as selected by software. Additional programming options are: P7 to P7 can assume UART1 and...
Page 34 2. Central Processing Unit(CPU) M16C/29 Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b8 b7 R0H(R0's high bits) R0L(R0's low bits)
Page 35 M16C/29 Group 2. Central Processing Unit(CPU) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed.
Page 36 M16C/29 Group 3. Memory 3. Memory Figure 3.1 is a memory map of the M16C/29 group. The linear address space of 1M bytes extends from address 00000 to FFFFF . From FFFFF down is ROM. For example, in the M30290F8HP,there are 64 Kbytes of internal ROM from F0000 to FFFFF The vector table for fixed interrupts, such as Reset and NMI, is mapped from FFFDC...
Page 37 M16C/29 Group 4. Special Function Register (SFR) MAP 4. Special Function Register (SFR) Map Register Symbol After reset Address 0000 0001 0002 0003 Processor mode register 0 0004 Processor mode register 1 00001000 0005 System clock control register 0 01001000 0006 System clock control register 1 00100000...
Page 38 M16C/29 Group 4. Special Function Register (SFR) MAP Register Symbol After reset Address 0040 CAN0 wakeup interrupt control register C01WKIC XXXX?000 0041 CAN0 successful reception interrupt control register C0RECIC XXXX?000 0042 CAN0 successful transmission interrupt control register C0TRMIC XXXX?000 0043 INT3 interrupt control register INT3IC XX00?000...
Page 39 M16C/29 Group 4. Special Function Register (SFR) MAP Register Symbol After reset Address CAN0 message box 2: Identifier/DLC XX?????? 0080 XX?????? 0081 0082 0083 0084 XX?????? 0085 CAN0 message box 2 : Data field 0086 0087 0088 0089 008A 008B 008C 008D CAN0 message box 2 : Time stamp...
Page 40 M16C/29 Group 4. Special Function Register (SFR) MAP Register Symbol After reset Address CAN0 message box 6: Identifier/DLC XX?????? 00C0 XX?????? 00C1 00C2 00C3 00C4 XX?????? 00C5 CAN0 message box 6 : Data field 00C6 00C7 00C8 00C9 00CA 00CB 00CC 00CD CAN0 message box 6 : Time stamp...
Page 41 M16C/29 Group 4. Special Function Register (SFR) MAP Register Symbol After reset Address CAN0 message box 10: Identifier/DLC XX?????? 0100 XX?????? 0101 0102 0103 0104 XX?????? 0105 CAN0 message box 10 : Data field 0106 0107 0108 0109 010A 010B 010C 010D CAN0 message box 10 : Time stamp...
Page 42 M16C/29 Group 4. Special Function Register (SFR) MAP Register Symbol After reset Address CAN0 message box 14: Identifier/DLC XX?????? 0140 XX?????? 0141 0142 0143 0144 XX?????? 0145 CAN0 message box 14 : Data field 0146 0147 0148 0149 014A 014B 014C 014D CAN0 message box 14 : Time stamp...
Page 43 M16C/29 Group 4. Special Function Register (SFR) MAP Register Symbol After reset Address CAN0 message control register 0 C0MCTL0 0200 CAN0 message control register 1 C0MCTL1 0201 CAN0 message control register 2 C0MCTL2 0202 CAN0 message control register 3 C0MCTL3 0203 CAN0 message control register 4 C0MCTL4...
Page 44 M16C/29 Group 4. Special Function Register (SFR) MAP Register Symbol After reset Address Time measurement, Pulse generation register 0 G1TM0,G1PO0 0300 0301 Time measurement, Pulse generation register 1 G1TM1,G1PO1 0302 0303 Time measurement, Pulse generation register 2 G1TM2,G1PO2 0304 0305 Time measurement, Pulse generation register 3 G1TM3,G1PO3 0306...
Page 45 M16C/29 Group 4. Special Function Register (SFR) MAP Register Symbol After reset Address 0340 0341 Timer A1-1 register TA11 0342 0343 Timer A2-1 register TA21 0344 0345 Timer A4-1 register TA41 0346 0347 Three phase PWM control register 0 INVC0 0348 Three phase PWM control register 1 INVC1...
Page 46 M16C/29 Group 4. Special Function Register (SFR) MAP Register Symbol After reset Address Count start flag TABSR 0380 Clock prescaler reset flag CPSRF 0XXXXXXX 0381 One-shot start flag ONSF 0382 Trigger select register TRGSR 0383 Up-dowm flag 0384 0385 Timer A0 register 0386 0387 Timer A1 register...
Page 47 M16C/29 Group 4. Special Function Register (SFR) MAP Register Symbol After reset Address A/D register 0 ???????? 03C0 XXXXXX?? 03C1 A/D register 1 ???????? 03C2 XXXXXX?? 03C3 A/D register 2 ???????? 03C4 XXXXXX?? 03C5 A/D register 3 ???????? 03C6 XXXXXX?? 03C7 A/D register 4 ????????
Page 48 M16C/29 Group 5. Reset 5. Reset There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscilla- tion stop detection reset. 5.1 Hardware Reset There are two types of hardware resets: a hardware reset 1 and a hardware reset 2. 5.1.1 Hardware Reset 1 ____________ ____________...
Page 49: Software Reset
M16C/29 Group 5. Reset Recommended operating voltage RESET RESET Equal to or less Equal to or less than 0.2V than 0.2V More than td(ROC) + td(P-R) Figure 5.1.1.1. Example Reset Circuit 5.2 Software Reset When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins, CPU, and SFR initialized.
Page 50 M16C/29 Group 5. Reset td(P-R) More than td(ROC) RESET CPU clock 28cycles CPU clock FFFFC Content of reset vector Address FFFFE Figure 5.1.1.2. Reset Sequence ____________ Table 5.1.1.1. Pin Status When RESET Pin Level is “L” Status Pin name P0 to P3, Input port (high impedance) P6 to P10 0000...
Page 51: Voltage Detection Circuit
M16C/29 Group 5. Reset 5.5 Voltage Detection Circuit Note 5.5 Voltage Detection Circuit is described in the Normal-ver. only as an example. This is assumed to use when VCC = 5V. Do not use this function in the T-ver. and V-ver. The voltage detection circuit monitors the voltage applied to the VCC pin in Vdet3 and Vdet 4.
Page 52 M16C/29 Group 5. Reset V o l t a g e D e t e c t i o n R e g i s t e r 1 ( 2 ) S y m b o l A d d r e s s A f t e r R e s e t 0 0 0 0 0 0 0...
Page 53 M16C/29 Group 5. Reset 5.0V 5.0V Vdet4 Vdet3r Vdet3 Vdet3s RESET Internal Reset Signal VC13 bit in Indefinite VCR1 register Set to “1” by program (reset level detect circuit enable) VC26 bit in Indefinite VCR2 register Set to “1” by program (voltage down detect circuit enable) VC27 bit in Indefinite...
Page 54: Voltage Down Detection Interrupt
M16C/29 Group 5. Reset 5.5.1 Voltage Down Detection Interrupt If the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled), the voltage down detection interrupt request is generated when the voltage applied to the VCC pin is above or below Vdet4.
Page 55 M16C/29 Group 5. Reset Voltage down detection interrupt generation circuit DF1, DF0 The D42 bit is set to “0” (not detected) by program. the VC27 bit is set to “0” Voltage Down Detection Circuit (voltage down detect circuit disabled), the D42 bit is set to “0”. D4INT clock(the VC27 clock with which it...
Page 56: Limitations On Exiting Stop Mode
M16C/29 Group 5. Reset 5.5.2 Limitations on Exiting Stop Mode The voltage down detection interrupt is immediately generated and the microcomputer exits stop mode if the CM10 bit in the CM1 register is set to “1” under the conditions below. •...
Page 57: Processor Mode
6. Processor Mode M16C/29 Group 6. Processor Mode This device functions in single-chip mode only. Figures 6.1 and 6.2 detail the associated registers. Processor mode register 0 (Note) Symbol Address After reset 0004 0000000 0 Bit symbol Bit name Function Reserved bit Should be set to "0".
Page 58: Clock Generation Circuit
7. Clock Generation Circuit M16C/29 Group 7. Clock Generation Circuit The clock generation circuit contains four oscillator circuits as follows: (1) Main clock oscillation circuit (2) Sub clock oscillation circuit (3) Variable on-chip oscillator (available at reset, oscillation stop detect function) (4) PLL frequency synthesizer Table 7.1 lists the clock generation circuit specifications.
Page 59 7. Clock Generation Circuit M16C/29 Group CCLK2-CCLK0=000 CCLK2-CCLK0=001 CCLK2-CCLK0=010 CCLK2-CCLK0=011 CCLK2-CCLK0=100 CAN module system clock divider PCLK5=0,CM01-CM00=00 I/O ports PCLK5=0,CM01-CM00=01 Sub-clock generating circuit PCLK5=1, PCLK5=0, COUT CM01-CM00=00 PCLK5=0, CM01-CM00=10 CM01-CM00=11 1/32 CM04 PCLK0=1 Sub-clock PCLK0=0 Variable On-chip ROCR0,ROCR1 oscillator on-chip ROCR2, ROCR3 clock oscillator...
Page 60 7. Clock Generation Circuit M16C/29 Group System clock control register 0 (Note 1) Symbol Address After reset 0006 01001000 Bit symbol Bit name Function Clock output function Refer to Table 7.5.3.1 Function of CLK CM00 select bit CM01 Wait Mode peripheral function 0 : Do not stop peripheral function clock in wait mode CM02 clock stop bit (Note 10)
Page 61 7. Clock Generation Circuit M16C/29 Group System clock control register 1 (Note 1) Symbol Address After reset 0007 00100000 Bit symbol Function name All clock stop control bit 0 : Clock on CM10 (Notes 4, 6) 1 : All clocks off (stop mode) System clock select bit 1 CM11 0 : Main clock...
Page 62 7. Clock Generation Circuit M16C/29 Group Oscillation stop detection register (Note 1) Symbol Address After reset 000C 0X000010 Bit symbol Bit name Function Oscillation stop, re- 0: Oscillation stop, re-oscillation CM20 detection function disabled oscillation detection bit 1: Oscillation stop, re-oscillation (Notes 7, 9, 10, 11) detection function enabled System clock select bit 2...
Page 63 7. Clock Generation Circuit M16C/29 Group Peripheral clock select register (Note) Symbol Address When reset PCLKR 025E 00000011 0 0 0 Bit name Function Bit symbol Timers A, B clock select bit 0 : f (Clock source for the timers 1 : f PCLK0 A, B, the timer S, the dead...
Page 64 7. Clock Generation Circuit M16C/29 Group PLL control register 0 (Note 1, Note 2) Symbol Address After reset PLC0 001C 0001 X010 Bit name Function symbol b1b0 PLL multiplying factor PLC00 0 0 0: Do not set select bit (Note 3) 0 0 1: Multiply by 2 0 1 0: Multiply by 4 0 1 1:...
Page 65: Main Clock
7. Clock Generation Circuit M16C/29 Group The following describes the clocks generated by the clock generation circuit. 7.1 Main Clock The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks.
Page 66: Sub Clock
7. Clock Generation Circuit M16C/29 Group 7.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. The sub clock oscillator circuit is configured by connecting a crystal resonator between the X and X COUT...
Page 67: On-Chip Oscillator Clock
7. Clock Generation Circuit M16C/29 Group 7.3 On-chip Oscillator Clock This clock is supplied by a variable on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit of PM2 register is “1” (on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer to “10.
Page 68 7. Clock Generation Circuit M16C/29 Group START Set the CM07 bit to “0” (main clock), the CM17 to CM16 bits to “00 ”(main clock undivided), and the CM06 bit to “0” (CM16 and CM17 bits enabled). (Note) Set the PLC02 to PLC00 bits (multiplying factor). (To select a 16 MHz or higher PLL clock) Set the PM20 bit to “0”...
Page 69: Cpu Clock And Peripheral Function Clock
7. Clock Generation Circuit M16C/29 Group 7.5 CPU Clock and Peripheral Function Clock The CPU clock is used to operate the CPU and peripheral function clocks are used to operate the periph- eral functions. 7.5.1 CPU Clock This is the operating clock for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock or the PLL clock.
Page 70: Power Control
7. Clock Generation Circuit M16C/29 Group 7.6 Power Control There are three power control modes. For convenience’ sake, all modes other than wait and stop modes are referred to as normal operation mode here. 7.6.1 Normal Operation Mode Normal operation mode is further classified into seven modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating.
Page 71: On-Chip Oscillator Mode
7. Clock Generation Circuit M16C/29 Group 7.6.1.6 On-chip Oscillator Mode The selected on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on, f can be used as the count source for timers A and B.
Page 72: Pin Status During Wait Mode
7. Clock Generation Circuit M16C/29 Group 7.6.2.3 Pin Status During Wait Mode The I/O port pins retain their status held just prior to wait mode. 7.6.2.4 Exiting Wait Mode ______ The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral func- tion interrupt.
Page 73: Stop Mode
7. Clock Generation Circuit M16C/29 Group 7.6.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode.
Page 74 7. Clock Generation Circuit M16C/29 Group Figure 7.6.1 shows the state transition from normal operation mode to stop mode and wait mode. Figure 7.6.1.1 shows the state transition in normal operation mode. Table 7.6.1 shows a state transition matrix describing allowed transition and setting. The vertical line shows current state and horizontal line shows state after transition.
Page 75 7. Clock Generation Circuit M16C/29 Group Main clock oscillation On-chip oscillator clock oscillation On-chip oscillator low power Middle-speed mode Middle-speed mode Middle-speed mode PLL operation mode Middle-speed mode On-chip oscillator mode PLC07=1 dissipation mode (divide by 4) (divide by 8) (divide by 16) High-speed mode (divide by 2)
Page 76 7. Clock Generation Circuit M16C/29 Group Table 7.6.1. Allowed Transition and Setting State after transition On-chip oscillator On-chip oscillator High-speed mode, Low-speed mode 2 Low power PLL operation low power mode 2 Stop mode Wait mode middle-speed mode mode dissipation mode dissipation mode (9) 7 (13) 3...
Page 77: System Clock Protective Function
7. Clock Generation Circuit M16C/29 Group 7.7 System Clock Protective Function When the main clock is selected for the CPU clock source, this function protects the clock from modifica- tions in order to prevent the CPU clock from becoming halted by run-away. If the PM21 bit of PM2 register is set to “1”...
Page 78: Operation When Cm27 Bit = 0 (Oscillation Stop Detection Reset)
7. Clock Generation Circuit M16C/29 Group 7.8.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) When main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to “SFR”, “Reset”).
Page 79: How To Use Oscillation Stop And Re-Oscillation Detect Function
7. Clock Generation Circuit M16C/29 Group 7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function • The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter- rupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
Page 80: Protection
M16C/29 Group 8. Protection 8. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by the PRCR register.
Page 81: Interrupts
M16C/29 Group 9. Interrupts 9. Interrupts 9.1 Type of Interrupts Figure 9.1.1 shows types of interrupts. Undefined instruction (UND instruction) Overflow (INTO instruction) Software BRK instruction (Non-maskable interrupt) INT instruction _______ ________ Interrupt DBC (Note 2) Watchdog timer Special Oscillation stop and re-oscillation (Non-maskable interrupt) detection Voltage down detection...
Page 82: Software Interrupts
M16C/29 Group 9. Interrupts 9.1.1 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non- maskable interrupts. 9.1.1.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 9.1.1.2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the operation resulted in an overflow).
Page 83: Hardware Interrupts
M16C/29 Group 9. Interrupts 9.1.2 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function inter- rupts. 9.1.2.1 Special Interrupts Special interrupts are non-maskable interrupts. _______ 9.1.2.1.1 NMI Interrupt _______ _______ An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details _______ about the NMI interrupt, refer to the section "NMI interrupt".
Page 84: Interrupts And Interrupt Vector
M16C/29 Group 9. Interrupts 9.2 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector.
Page 85: Relocatable Vector Tables
M16C/29 Group 9. Interrupts 9.2.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 9.2.2.1 lists the relocatable vector tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses.
Page 86: Interrupt Control
M16C/29 Group 9. Interrupts 9.3 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the FLG register’s I flag, IPL, and each interrupt control register’s ILVL2 to ILVL0 bits to enable/ disable the maskable interrupts.
Page 87 M16C/29 Group 9. Interrupts Interrupt control register (Note 2) Symbol Address After reset C01WKIC 0041 XXXXX000 C0RECIC 0042 XXXXX000 C0TRMIC 0043 XXXXX000 ICOC0IC 0045 XXXXX000 ICOC1IC, IICIC (Note 3) 0046 XXXXX000 BTIC, SCLDAIC (Note 3) 0047 XXXXX000 BCNIC 004A XXXXX000 DM0IC, DM1IC 004B , 004C...
Page 88 M16C/29 Group 9. Interrupts Interrupt request cause select register Symbol Address After reset IFSR 035F Bit name Function Bit symbol IFSR0 INT0 interrupt polarity 0 : One edge switching bit 1 : Both edges (Note 1) IFSR1 INT1 interrupt polarity 0 : One edge switching bit 1 : Both edges...
Page 89: I Flag
M16C/29 Group 9. Interrupts 9.3.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts. 9.3.2 IR Bit The IR bit is set to “1”...
Page 90: Interrupt Sequence
M16C/29 Group 9. Interrupts 9.4 Interrupt Sequence An interrupt sequence (the device behavior from the instant an interrupt is accepted to the instant the interrupt routine is executed) is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
Page 91: Interrupt Response Time
M16C/29 Group 9. Interrupts 9.4.1 Interrupt Response Time Figure 9.4.1.1 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of the time from when an interrupt request is generated till when the instruction then executing is completed ((a) in Figure 9.4.1.1) and the time during which the interrupt sequence is executed ((b) in Figure 9.4.1.1).
Page 92: Saving Registers
M16C/29 Group 9. Interrupts 9.4.3 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, 16 bits in total, are saved to the stack first.
Page 93 M16C/29 Group 9. Interrupts The operation of saving registers carried out in the interrupt sequence is dependent on whether the (Note) (Note) , at the time of acceptance of an interrupt request, is even or odd. If the stack pointer even, the FLG register and the PC are saved, 16 bits at a time.
Page 94: Returning From An Interrupt Routine
M16C/29 Group 9. Interrupts 9.4.4 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Page 95 M16C/29 Group 9. Interrupts Priority level of each interrupt Level 0 (initial value) Highest INT1 Timer B2 Timer B0 Timer A3 Timer A1 ICOC interrupt 1, I C bus interface INT3 INT2 INT0 Timer B1 Timer A4 Timer A2 ICOC base timer, S ICOC interrupt 0 UART1 reception UART0 reception...
Page 96: Int Interrupt
M16C/29 Group 9. Interrupts ______ 9.6 INT Interrupt _______ INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSR register's IFSRi bit. ________ ________ ________ To use the INT4 interrupt, set the IFSR register's IFSR6 bit to "1" (=INT4). To use the INT5 interrupt, set the ________ IFSR register's IFSR7 bit to "1"...
Page 97: Key Input Interrupt
M16C/29 Group 9. Interrupts 9.8 Key Input Interrupt A key input interrupt is generated when input on any of the P10 to P10 pins which has had the PD10 register’s PD10_4 to PD10_7 bits set to “0” (= input) goes low. Key input interrupts can be used for a key- on wakeup function to get the microcomputer to exit stop or wait modes.
Page 98: Address Match Interrupt
M16C/29 Group 9. Interrupts 9.10 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi register.
Page 99 M16C/29 Group 9. Interrupts Address match interrupt enable register Symbol Address After reset AIER 0009 XXXXXX00 Bit symbol Bit name Function Address match interrupt 0 0 : Interrupt disabled AIER0 enable bit 1 : Interrupt enabled Address match interrupt 1 AIER1 0 : Interrupt disabled enable bit...
Page 100: Watchdog Timer
M16C/29 Group 10. Watchdog Timer 10. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom- mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler.
Page 101 M16C/29 Group 10. Watchdog Timer Setting the PM22 bit to “1” results in the following conditions • The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source. Watchdog timer count (32768) Watchdog timer period = on-chip oscillator clock •...
Page 102: Cold Start / Warm Start
M16C/29 Group 10. Watchdog Timer 10.2 Cold start / Warm start The WDC5 flag in the WDC register indicates the last reset by power on (cold start) or by reset signal (warm start). The WDC5 flag is set “0” at power on, and is set “1” at writing any data to the WDC register. The flag is not set to “0”...
Page 103: Dmac
11. DMAC M16C/29 Group 11. DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the source address to the destination address. The DMAC uses the same data bus as used by the CPU.
Page 104 11. DMAC M16C/29 Group Table 11.1 DMAC Specifications Item Specification No. of channels 2 (cycle steal method) Transfer memory space • From any address in the 1M bytes space to a fixed address • From a fixed address to any address in the 1M bytes space •...
Page 105 11. DMAC M16C/29 Group DMA0 request cause select register Symbol Address After reset DM0SL 03B8 Bit symbol Function Bit name DSEL0 DMA request cause Refer to note select bit DSEL1 DSEL2 DSEL3 Nothing is assigned. When write, set to “0”. When read, its content is “0”.
Page 106 11. DMAC M16C/29 Group DMA1 request cause select register Symbol Address After reset DM1SL 03BA Bit name Function Bit symbol DSEL0 DMA request cause Refer to note select bit DSEL1 DSEL2 DSEL3 Nothing is assigned. When write, set to “0”. (b5-b4) When read, its content is “0”.
Page 107 11. DMAC M16C/29 Group DMAi source pointer (i = 0, 1) (Note) (b19) (b16)(b15) (b8) (b23) Symbol Address After reset SAR0 0022 to 0020 Indeterminate SAR1 0032 to 0030 Indeterminate Setting range Function Set the source address of transfer 00000 to FFFFF Nothing is assigned.
Page 108: Transfer Cycles
11. DMAC M16C/29 Group 11.1 Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer.
Page 109 11. DMAC M16C/29 Group (1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address CPU clock Address Dummy Destination CPU use Source CPU use cycle RD signal WR signal Data Dummy Destination CPU use Source...
Page 110: Dma Transfer Cycles
11. DMAC M16C/29 Group 11.2. DMA Transfer Cycles Any combination of even or odd transfer read and write adresses is possible. Table 11.2.1 shows the number of DMA transfer cycles. Table 11.2.2 shows the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No.
Page 111: Dma Enable
11. DMAC M16C/29 Group 11.3 DMA Enable When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register is “1”...
Page 112: Channel Priority And Dma Transfer Timing
11. DMAC M16C/29 Group 11.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of CPU clock), the DMAS bit on each channel is set to “1”...
Page 113: Timers
M16C/29 Group 12.1 Timer A 12. Timers Eight 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (three). The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc.
Page 114 M16C/29 Group 12.1 Timer A PCLK0 bit = 0 Clock prescaler • Main clock 1 or • PLL clock 1/32 PCLK0 bit = 1 • On-chip Reset oscillator clock Set the CPSR bit of CPSRF register to “1” (= prescaler reset) 1 or Timer B2 overflow or underflow ( to Timer A count source)
Page 115: Timer A
M16C/29 Group 12.1 Timer A 12.1 Timer A Figure 12.1.1 shows a block diagram of the timer A. Figures 12.1.2 to 12.1.4 show registers related to the timer A. The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same function.
Page 116 M16C/29 Group 12.1 Timer A Timer Ai register (i= 0 to 4) (Note 1) Symbol Address After reset (b15) (b8) 0387 , 0386 Indeterminate b0 b7 0389 , 0388 Indeterminate 038B , 038A Indeterminate 038D , 038C Indeterminate 038F , 038E Indeterminate Mode Function...
Page 117 M16C/29 Group 12.1 Timer A One-shot start flag Symbol Address After reset ONSF 0382 Bit symbol Bit name Function Timer A0 one-shot start flag TA0OS The timer starts counting by setting this bit to “1” while the TMOD1 to Timer A1 one-shot start flag TA1OS TMOD0 bits of TAiMR register (i = 0 to 4) = ‘10...
Page 118: Timer Mode
M16C/29 Group 12.1 Timer A 12.1.1. Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.1.1.1). Figure 1.2.1.1.1 shows TAiMR register in timer mode. Table 12.1.1.1. Specifications in Timer Mode Item Specification Count source Count operation •...
Page 119: Event Counter Mode
M16C/29 Group 12.1 Timer A 12.1.2. Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 12.1.2.1 lists specifica- tions in event counter mode (when not processing two-phase pulse signal).
Page 120 M16C/29 Group 12.1 Timer A Timer Ai mode register (i=0 to 4) (When not using two-phase pulse signal processing) Symbol Address After reset TA0MR to TA4MR 0396 to 039A Bit symbol Bit name Function TMOD0 Operation mode select bit b1 b0 0 1 : Event counter mode (Note 1) TMOD1 0 : Pulse is not output...
Page 121 M16C/29 Group 12.1 Timer A Table 12.1.2.2. Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4) Item Specification Count source • Two-phase pulse signals input to TAi or TAi pins (i = 2 to 4) Count operation •...
Page 122 M16C/29 Group 12.1 Timer A Timer Ai mode register (i=2 to 4) (When using two-phase pulse signal processing) Symbol Address After reset TA2MR to TA4MR 0398 to 039A Bit name Function TMOD0 b1 b0 Operation mode select bit 0 1 : Event counter mode TMOD1 To use two-phase pulse signal processing, set this bit to “0”.
Page 123: Counter Initialization By Two-Phase Pulse Signal Processing
M16C/29 Group 12.1 Timer A 12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two- phase pulse signal processing. This function can only be used in timer A3 event counter mode during two-phase pulse signal process- _______ ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Page 124: One-Shot Timer Mode
M16C/29 Group 12.1 Timer A 12.1.3. One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. (See Table 12.1.3.1.) When the trigger occurs, the timer starts up and continues operating for a given period. Figure 12.1.3.1 shows the TAiMR register in one-shot timer mode.
Page 125 M16C/29 Group 12.1 Timer A Timer Ai mode register (i=0 to 4) Symbol Address After reset TA0MR to TA4MR to 039A Bit symbol Bit name Function TMOD0 b1 b0 Operation mode select bit 1 0 : One-shot timer mode TMOD1 Pulse output function 0 : Pulse is not output select bit...
Page 126: Pulse Width Modulation (Pwm) Mode
M16C/29 Group 12.1 Timer A 12.1.4. Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession (see Table 12.1.4.1). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 12.1.4.1 shows TAiMR register in pulse width modulation mode.
Page 127 M16C/29 Group 12.1 Timer A Timer Ai mode register (i= 0 to 4) Symbol Address After reset TA0MR to TA4MR 0396 to 039A Bit symbol Bit name Function b1 b0 TMOD0 Operation mode 1 1 : PWM mode select bit TMOD1 Must be set to “1”...
Page 128 M16C/29 Group 12.1 Timer A 1 / f – 1) Count source “H” Input signal to “L” Trigger is not generated by this signal 1 / f “H” PWM pulse output from TA iOUT “L” IR bit of TAiIC “1” register “0”...
Page 129: Timer B
12.2 Timer B M16C/29 Group 12.2 Timer B Figure 12.2.1 shows a block diagram of the timer B. Figures 12.2.2 and 12.2.3 show registers related to the timer B. Timer B supports the following four modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to 2) to select the desired mode.
Page 130 12.2 Timer B M16C/29 Group Timer Bi register (i=0 to 2)(Note 1) Symbol Address After reset 0391 , 0390 Indeterminate (b15) (b8) b0 b7 0393 , 0392 Indeterminate 0395 , 0394 Indeterminate Mode Function Setting range Timer mode Divide the count source by n + 1 0000 to FFFF where n = set value...
Page 131: Timer Mode
12.2 Timer B M16C/29 Group 12.2.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.2.1.1). Figure 12.2.1.1 shows TBiMR register in timer mode. Table 12.2.1.1 Specifications in Timer Mode Item Specification Count source Count operation •...
Page 132: Event Counter Mode
12.2 Timer B M16C/29 Group 12.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 12.2.2.1) . Figure 12.2.2.1 shows TBiMR register in event counter mode. Table 12.2.2.1 Specifications in Event Counter Mode Item Specification...
Page 133: Pulse Period And Pulse Width Measurement Mode
12.2 Timer B M16C/29 Group 12.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see Table 12.2.3.1). Figure 12.2.3.1 shows TBiMR register in pulse period and pulse width measurement mode.
Page 134 12.2 Timer B M16C/29 Group Count source “H” Measurement pulse “L” Transfer Transfer (indeterminate value) (measured value) Reload register counter transfer timing (Note 1) (Note 1) (Note 2) Timing at which counter reaches “0000 ” “1” TBiS bit “0” “1” TBiIC register's IR bit “0”...
Page 135: A/D Trigger Mode
12.2 Timer B M16C/29 Group 12.2.4 A/D Trigger Mode A/D trigger mode is used as conversion start trigger for A/D converter in simultaneous sample sweep mode of A/D conversion or delayed trigger mode 0. This mode is used as conversion start triger of A/D converter.
Page 136 12.2 Timer B M16C/29 Group Timer Bi mode register (i= 0 to 1) Symbol Address After reset TB0MR to TB1MR 039B to 039C 00XX0000 Bit symbol Bit name Function TMOD0 b1 b0 Operation mode select bit 0 0 : Timer mode or A/D trigger mode TMOD1 Invalid in A/D trigger mode Either "0"...
Page 137: Three-Phase Motor Control Timer Function
12.3 Three-phase Motor Control Timer Function M16C/29 Group 12.3 Three-phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 12.3.1 lists the specifications of the three-phase motor control timer function. Figure 12.3.1 shows the block diagram for three-phase motor control timer function.
Page 138 M16C/29 Group 12.3 Three-phase Motor Control Timer Function Figure 12.3.1. Three-phase Motor Control Timer Functions Block Diagram Rev.1.00 Nov 01,2004 page 118 of 402 REJ09B0101-0100Z...
Page 139 12.3 Three-phase Motor Control Timer Function M16C/29 Group Three-phase PWM control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset INVC0 0348 Bit symbol Bit name Description Effective interrupt output 0: ICTB2 counter incremented by 1 at INV00 polarity select bit odd-numbered occurrences of a timer...
Page 140 M16C/29 Group 12.3 Three-phase Motor Control Timer Function Three-phase PWM control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset INVC1 0349 Bit symbol Bit name Description Timer A1, A2, A4 start 0: Timer B2 underflow INV10 trigger signal select bit 1: Timer B2 underflow and write to the...
Page 141 12.3 Three-phase Motor Control Timer Function M16C/29 Group Three-phase output buffer register(i=0,1) (Note) Symbol Address When reset IDB0 034A IDB1 034B Bit name Function Write the output level U phase output buffer i 0: Active level 1: Inactive level DUBi U phase output buffer i When read, these bits show the three-phase V phase output buffer i...
Page 142 M16C/29 Group 12.3 Three-phase Motor Control Timer Function Timer Ai, Ai-1 register (i=1, 2, 4) (Note 1, Note 2, Note 3, Note 4, Note 5) Symbol Address After reset 0389 -0388 ???? 038B -038A ???? (b15) (b8) 038F -038E ???? b0 b7 TA11 (Note6,7) 0343 -0342...
Page 143 12.3 Three-phase Motor Control Timer Function M16C/29 Group Timer B2 special mode register (Note 1) Symbol Address After reset TB2SC 039E X0000000 Bit symbol Bit name Function 0 : Timer B2 underflow PWCON Timer B2 Reload Timing Switch Bit (Note 2) 1 : Timer A output at odd-numbered Three-Phase Output Port 0 : Three-phase output forcible cutoff...
Page 144 M16C/29 Group 12.3 Three-phase Motor Control Timer Function Timer B2 register (Note ) Symbol Address After reset (b15) (b8) 0395 -0394 Indeterminate b0 b7 Function Setting range 0000 to FFFF Divide the count source by n + 1 where n = set value. Timer A1, A2 and A4 are started at every occurrence of underflow.
Page 145 12.3 Three-phase Motor Control Timer Function M16C/29 Group Timer Ai mode register Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 TA1MR 0397 TA2MR 0398 TA4MR 039A Bit symbol Bit name Function TMOD0 Must set to “10 ”...
Page 146 M16C/29 Group 12.3 Three-phase Motor Control Timer Function The three-phase motor control timer function is enabled by setting the INV02 bit of INVC0 register to “1”. When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to control three-phase PWM outputs (U, U, V, V, W and W).
Page 147 12.3 Three-phase Motor Control Timer Function M16C/29 Group Carrier wave: sawtooth waveform Carrier wave Signal wave Timer B2 Start trigger signal for timer A4* Timer A4 one-shot pulse* Rewriting IDB0, IDB1 registers Transfer to three-phase output shift register U phase output signal * U phase output signal *...
Page 148: Position-Data-Retain Function
M16C/29 Group 12.3 Three-phase Motor Control Timer Function 12.3.1 Position-data-retain Function This function is used to retain the position data synchronously with the three-phase waveform output.There are three position-data input pins for U, V, and W phases. A trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected by the retain-trigger polarity select bit(bit 3 of the position-data-retain function control register, at address 034E ).
Page 149: Position-Data-Retain Function Control Register
12.3 Three-phase Motor Control Timer Function M16C/29 Group 12.3.1.2 Position-data-retain Function Control Register Figure 12.3.1.2.1 shows the structure of the position-data-retain function contol register. Position-data-retain function control register (Note) Symbol Address When reset PDRF 034E XXXX 0000 Bit name Function Input level at pin IDW is read out.
Page 150: Three-Phase/Port Output Switch Function
M16C/29 Group 12.3 Three-phase Motor Control Timer Function 12.3.2 Three-phase/Port Output Switch Function When the INVC03 bit in the INVC0 register set to “1”(Timer output enabled for three-phase motor control) and setting the PFCi (i=0 to 5) in the PFCR register to “0”(I/O port), the three-phase PWM output pin (U, U, V, V, W and W) functions as I/O port.
Page 151 12.3 Three-phase Motor Control Timer Function M16C/29 Group Port function control register (Note) Symbol Address When reset PFCR 0358 0011 1111 Bit name Function 0: Input/Output port P8 Port P8 output PFC0 1: Three-phase PWM output function select bit (U phase output) 0: Input/Output port P8 Port P8 output...
Page 152: Timer S (Input Capture/Output Compare)
M16C/29 Group 13. Timer S (Input Capture / Output Compare) 13. Timer S (Input Capture/Output Compare) The Timer S (Input Capture/Output Compare : here after, Timer S is referred to as "IC/OC".) is a multi- functional I/O port for time measurement and waveform generation. Each channel of the IC/OC module provides the capability for time measurement, by input capture, and also provides the capability for wave- form generation, by output comparison.
Page 153 M16C/29 Group 13. Timer S (Input Capture / Output Compare) Figure 13.1 shows the block diagram of the IC/OC. PCLK0=0 Main clock, PLL clock, or f On-chip PCLK0=1 oscillator clock Request by matching G1BTRR and base timer Request by matching G1PO0 register and base timer Request from INT1 pin Base timer reset BCK1 to BCK0...
Page 154 M16C/29 Group 13. Timer S (Input Capture / Output Compare) Figures 13.2 to 13.11 show registers associated with the IC/OC base timer, the time measurement function, and the waveform generation function. Base timer register (Note 1) (b7) (b0) Symbol Address When reset G1BT 0321...
Page 155 M16C/29 Group 13. Timer S (Input Capture / Output Compare) Divider register Symbol Address When reset G1DV 032A Function Setting range This register determines the divide ratio of the to FF selected clock source (f1, f2 or two pulse input). The selected clock source is divided by (n+1).
Page 156 M16C/29 Group 13. Timer S (Input Capture / Output Compare) Base timer control register 1 Symbol Address When reset G1BCR1 0323 0000 0000 Bit name Function symbol Reserved bit Should be set to "0". (b0) 0: The base timer is not reset by Base timer reset matching the G1PO0 register RST1...
Page 157 M16C/29 Group 13. Timer S (Input Capture / Output Compare) Base timer reset register (Note 1) (b7) (b0) Symbol Address When reset G1BTRR 0329 - 0328 ???? Function Setting range When enabled by the RST4 reset cause bit 0000 to FFFF (bit 2 of G1BCR0), the G1BTRR will reset the Base Timer, G1BT, when G1BT matches G1BTRR...
Page 158 M16C/29 Group 13. Timer S (Input Capture / Output Compare) Time measurement control register j (j=0 to 7) Symbol Address When reset G1TMCR0 to G1TMCR3 0318 , 0319 , 031A , 031B 0000 0000 G1TMCR4 to G1TMCR7 031C , 031D , 031E , 031F 0000 0000...
Page 159 M16C/29 Group 13. Timer S (Input Capture / Output Compare) Time measurement register j (j=0 to 7) (b0) (b7) Symbol Address When reset G1TM0 to G1TM2 0301 - 0300 0303 - 0302 0305 - 0304 ???? G1TM3 to G1TM5 0307 - 0306 0309 - 0308...
Page 160 M16C/29 Group 13. Timer S (Input Capture / Output Compare) Waveform generation register j (j=0 to 7) Symbol Address When reset (b0) (b7) G1PO0 to G1PO2 0301 -0300 0303 -0302 0305 -0304 ???? G1PO3 to G1PO5 0307 -0306 0309 -0308 030B -030A ????
Page 161 M16C/29 Group 13. Timer S (Input Capture / Output Compare) Function select register Symbol Address When reset G1FS 0327 0000 0000 Bit name Function symbol Channel 0 time measure- 0 : Select the waveform generation ment/waveform generation FSC0 function function select bit 1 : Select the time measurement function Channel 1 time measure-...
Page 162 M16C/29 Group 13. Timer S (Input Capture / Output Compare) Interrupt request register (Notes 1) Symbol Address When reset G1IR 0330 ???? ???? Bit name Function symbol 0 : No Request G1IR0 Interrupt Request, Ch0 1 : Interrupt Requested G1IR1 Interrupt Request, Ch1 G1IR2 Interrupt Request, Ch2...
Page 163 M16C/29 Group 13. Timer S (Input Capture / Output Compare) Interrupt enable register 0 Symbol Address When reset G1IE0 0331 0000 0000 Bit name Function symbol 0 : IC/OC interrupt 0 request disable G1IE00 Interrupt Enable 0, CH0 1 : IC/OC interrupt 0 request enable G1IE01 Interrupt Enable 0, CH1 G1IE02...
Page 164: Base Timer
M16C/29 Group 13. Timer S (Input Capture / Output Compare) 13.1 Base Timer The base timer counts an internally generated count source with free-running. Table 13.1.1 lists specifications of the base timer. Table 13.1.2 shows registers associated with the base timer.
Page 165 M16C/29 Group 13. Timer S (Input Capture / Output Compare) BCK1 to BCK0 or f (n+1) divider Base timer b14 b15 Two-phase pulse input (Note 1) Overflow signal Base timer BTS bit in G1BCR1 register overflow request RST4 Matched with G1BTRR RST1 Base timer reset Matched with G1PO0 register...
Page 166 M16C/29 Group 13. Timer S (Input Capture / Output Compare) FFFF C000 State of a counter 8000 4000 0000 IT=1 in the G1BCR0 register (Base timer interrupt generated by the bit 14 overflow) "1" b14 overflow signal "0" Base Timer interrupts IT=0 in the G1BCR0 register (Base timer interrupt generated by the bit 15 overflow)
Page 167 M16C/29 Group 13. Timer S (Input Capture / Output Compare) (1) When the base timer is reset while the base timer increments the counter (A-phase) Input waveform min 1 µs min 1 µs (B-phase) When selects no division (n+1) divisor (Note 1) INT1 (Z-phase) Base timer starts counting...
Page 168: Base Timer Reset Register
M16C/29 Group 13. Timer S (Input Capture / Output Compare) 13.1.1 Base Timer Reset Register The Base Timer Reset Register(G1BTRR) provides the capability to reset the Base Timer(BT) when the base timer count value matches the value stored in the G1BTRR. The G1BTRR is enabled by the RST4 reset cause select bit,G1BCR0(2).
Page 169: Interrupt Operation
M16C/29 Group 13. Timer S (Input Capture / Output Compare) 13.2 Interrupt Operation The IC/OC interrupt contains several request causes. Figure 13.2.1 shows the IC/OC interrupt block dia- gram and Table 13.2.1 shows the IC/OC interrupt assignation. When either the base timer reset request or base timer overflow request is generated, the IR bit (bit 3 in the BTIC register) corresponding to the IC/OC base timer interrupt is set to "1"...
Page 170: Time Measurement Function
M16C/29 Group 13. Timer S (Input Capture / Output Compare) 13.4 Time Measurement Function Synchronizing with an external trigger input, the value of the base timer is stored into the G1TMj register (j=0 to 7). Table 13.4.1 shows specifications of the time measurement function. Table 13.4.2 shows regis- ter settings associated with the time measurement function.
Page 171 M16C/29 Group 13. Timer S (Input Capture / Output Compare) Table 13.4.2. Register Settings Associated with the Time Measurement Function Register Function G1TMCRj CTS1 to CTS0 Select time measurement trigger DF1 to DF0 Select the digital filter function GT, GOC, GSC Select the gate function Select the prescaler function G1TPRk...
Page 172 M16C/29 Group 13. Timer S (Input Capture / Output Compare) When selecting the rising edge for timer measurement trigger (The CTS1 to CTS0 bits in the G1TMCR register (j=0 to 7)=01 Base timer n+9 n+10 n+11 n+12 n+13 n+14 (Note 2) INPC1j pin input or trigger signal after passing the digital...
Page 173 M16C/29 Group 13. Timer S (Input Capture / Output Compare) (a) When using the prescaler function (When the G1TPRj register (j=6, 7) =02 , PR bit in the G1TMCRj register (j=6, 7) =1) Base timer n+9 n+10 n+11 +12 n+13 n+14 INPC1j pin input or trigger signal after...
Page 174: Waveform Generation Function
M16C/29 Group 13. Timer S (Input Capture / Output Compare) 13.5 Waveform Generation Function Waveforms are generated when value of the base timer matches G1POj register (j=0 to 7). The waveform generation function has the following three modes : • Single-phase waveform output mode •...
Page 175: Single-Phase Waveform Output Mode
M16C/29 Group 13. Timer S (Input Capture / Output Compare) 13.5.1 Single-Phase Waveform Output Mode Output level of the OUTC1j pin is inverted when value of the base timer matches that of the G1POj register (j=0 to 7). The inverted output level is returned to a default output level when the base timer reaches "0000 ".
Page 176 M16C/29 Group 13. Timer S (Input Capture / Output Compare) (1) Free-running operation (Bits RST4, RST2, and RST1 of the G1BCR0 and G1BCR1 registers are set to "0") FFFF Base timer 0000 65536-m Inverse Inverse OUTC1j pin Return to initial output level 65536 When setting to "0", write "0"...
Page 177: Phase-Delayed Waveform Output Mode
M16C/29 Group 13. Timer S (Input Capture / Output Compare) 13.5.2 Phase-Delayed Waveform Output Mode Output level of the OUTC1j pin is inverted whenever the value of the base timer matches that of the G1POj register value ( j=0 to 7). Table 13.5.2.1 lists specifications of phase-delayed waveform mode. Figure 13.5.2.1 lists an example of phase-delayed waveform mode operation.
Page 178 M16C/29 Group 13. Timer S (Input Capture / Output Compare) (1) Free-running operation (Bits RST4, RST2, and RST1 of the G1BCR0 and G1BCR1 registers are set to "0") FFFF Base timer 0000 65536 65536 Inverse OUTC1j pin Inverse 65536X2 When setting to "0", write "0"...
Page 179: Set/Reset Waveform Output (Sr Waveform Output) Mode
M16C/29 Group 13. Timer S (Input Capture / Output Compare) 13.5.3 Set/Reset Waveform Output (SR Waveform Output) Mode Output level of the OUTC1j pin is inverted when the base timer value matches that of the G1POj register value (j=0, 2, 4, 6). It is returned to default output level when the base timer value matches that of the G1POk register (k=j+1).
Page 180 M16C/29 Group 13. Timer S (Input Capture / Output Compare) (1) Free-running operation (The RST1 bit is set to "1", and both RST4 and RST2 bits are set to "0") FFFF Base timer 0000 65536-n+m Return to initial output level OUTC1j pin Inverse Inverse...
Page 181: I/O Port Function Select
M16C/29 Group 13. Timer S (Input Capture / Output Compare) 13.6 I/O Port Function Select The M16C/29 will automatically configure the port package pins to be IC/OC inputs or outputs based on the values in the Function Enable (G1FE) and Function Select (G1FS) registers. When using PWM S-R mode, two channels are enabled and selected as output, but only one output, the output corresponding to the even numbered channel, is generated.
Page 182: Inpc17 Alternate Input Pin Selection
M16C/29 Group 13. Timer S (Input Capture / Output Compare) 13.6.1 INPC1 Alternate Input Pin Selection The input capture pin for IC/OC channel 7 can be assigned to one of two package pins. Control bit, G1BCR0(6) CH7INSEL, Channel 7 input select, selects IC/OC INPC1 to come from P2 ________ OUTC1...
Page 183: Serial I/O
M16C/29 Group 14.1 UARTi (i=0 to 2) 14. Serial I/O Serial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4. SI/O4 is not in 64 pin version. 14.1. UARTi (i=0 to 2) UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Page 184 M16C/29 Group 14.1 UARTi (i=0 to 2) PCLK1=0 2SIO 1SIO or 2SIO 1SIO Main clock or on-chip oscillator clock PCLK1=1 8SIO 32SIO (UART0) UART reception Clock source selection Receive 1/16 Reception clock CLK1 to CLK0 Clock synchronous control circuit Transmit/ type U0BRG 1SIO or...
Page 185 M16C/29 Group 14.1 UARTi (i=0 to 2) Clock synchronous type UART (7 bits) disabled UART (8 bits) Clock UARTi receive register synchronous UART (7 bits) type STPS=0 PRYE=0 RxDi STPS=1 UART PRYE=1 UART (9 bits) enabled Clock synchronous type UART (8 bits) UART (9 bits) UARTi receive buffer register...
Page 186 M16C/29 Group 14.1 UARTi (i=0 to 2) No reverse IOPOL=0 RxD data RxD2 reverse circuit IOPOL=1 Reverse Clock synchronous type UART (7 bits) disabled UART Clock UARTi receive register UART(7 bits) (8 bits) synchronous STPS=0 PRYE=0 type STPS=1 PRYE=1 Clock UART UART synchronous type...
Page 187 M16C/29 Group 14.1 UARTi (i=0 to 2) UARTi transmit buffer register (i=0 to 2)(Note) Symbol Address After reset (b15) (b8) U0TB 03A3 -03A2 Indeterminate U1TB 03AB -03AA Indeterminate U2TB 037B -037A Indeterminate Function Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Use MOV instruction to write to this register.
Page 188 M16C/29 Group 14.1 UARTi (i=0 to 2) UARTi transmit/receive mode register (i=0, 1) Symbol Address After reset U0MR, U1MR 03A0 , 03A8 Function Bit name symbol SMD0 b2 b1 b0 Serial I/O mode select bit 0 0 0 : Serial I/O disabled (Note 2) 0 0 1 : Clock synchronous serial I/O mode 1 0 0 : UART mode transfer data 7 bits long...
Page 189 M16C/29 Group 14.1 UARTi (i=0 to 2) UARTi transmit/receive control register 0 (i=0 to 2) Symbol Address After reset U0C0 to U2C0 03A4 , 03AC , 037C 00001000 Bit name Function symbol b1 b0 CLK0 BRG count source 0 0 : f or f is selected 1SIO...
Page 190 M16C/29 Group 14.1 UARTi (i=0 to 2) UARTi transmit/receive control register 1 (i=0, 1) Symbol Address After reset b2 b1 U0C1, U1C1 03A5 ,03AD 00000010 Function Bit name symbol Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled Transmit buffer 0 : Data present in UiTB register empty flag...
Page 191 M16C/29 Group 14.1 UARTi (i=0 to 2) UART2 special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset U2SMR 0377 X0000000 Function symbol name IICM C mode select bit 0 : Other than I C bus mode 1 : I C bus mode Arbitration lost detecting...
Page 192 M16C/29 Group 14.1 UARTi (i=0 to 2) UART2 special mode register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset U2SMR3 0375 000X0X0X Bit name Function symbol Nothing is assigned. (b0) When write, set “0”. When read, its content is indeterminate. CKPH Clock phase set bit 0 : Without clock delay...
Page 193: Clock Synchronous Serial I/O Mode
M16C/29 Group 14.1 UARTi (i=0 to 2) 14.1.1. Clock Synchronous serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 14.1.1.1 lists the specifications of the clock synchronous serial I/O mode. Table 14.1.1.2 lists the registers used in clock synchronous serial I/O mode and the register values set.
Page 194 M16C/29 Group 14.1 UARTi (i=0 to 2) Table 14.1.1. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Function UiTB(Note3) 0 to 7 Set transmission data UiRB(Note3) 0 to 7 Reception data can be read Overrun error flag UiBRG 0 to 7...
Page 195 M16C/29 Group 14.1 UARTi (i=0 to 2) Table 14.1.1.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 14.3 shows pin functions for the case where the multiple transfer clock output pin select function is dese- lected.
Page 196 M16C/29 Group 14.1 UARTi (i=0 to 2) (1) Example of transmit timing Transfer clock “1” UiC1 register “0” Write data to the UiTB register TE bit “1” UiC1 register TI bit “0” Transferred from UiTB register to UARTi transmit register “H”...
Page 197: Clk Polarity Select Function
M16C/29 Group 14.1 UARTi (i=0 to 2) 14.1.1.1 CLK Polarity Select Function Use the UiC0 register (i = 0 to 2)’s CKPOL bit to select the transfer clock polarity. Figure 14.1.1.1.1 shows the polarity of the transfer clock. (1) When the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) (Note 2) (2) When the UiC0 register’s CKPOL bit = 1 (transmit data output at the rising...
Page 198: Continuous Receive Mode
M16C/29 Group 14.1 UARTi (i=0 to 2) 14.1.1.3 Continuous receive mode When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the UiC1 register’s TI bit is set to “0” (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not write dummy data to the UiTB register in a program.
Page 199: Cts/Rts Separate Function (Uart0)
M16C/29 Group 14.1 UARTi (i=0 to 2) _______ _______ 14.1.1.6 CTS/RTS separate function (UART0) _______ _______ _______ _______ This function separates CTS /RTS , outputs RTS from the P6 pin, and accepts as input the CTS from the P6 pin. To use this function, set the register bits as shown below. _______ _______ •...
Page 200: Clock Asynchronous Serial I/O (Uart) Mode
M16C/29 Group 14.1 UARTi (i=0 to 2) 14.1.2. Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 14.1.2.1 lists the specifications of the UART mode. Table 14.1.2.1.
Page 201 M16C/29 Group 14.1 UARTi (i=0 to 2) Table 14.1.2.2. Registers to Be Used and Settings in UART Mode Register Function UiTB 0 to 8 Set transmission data (Note 1) UiRB 0 to 8 Reception data can be read (Note 1) OER,FER,PER,SUM Error flag UiBRG 0 to 7...
Page 202 M16C/29 Group 14.1 UARTi (i=0 to 2) Table 14.1.2.3 lists the functions of the input/output pins during UART mode. Table 14.1.2.4 lists the P6 pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”.
Page 203 M16C/29 Group 14.1 UARTi (i=0 to 2) • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to “L”. Transfer clock UiC1 register “1”...
Page 204: Lsb First/Msb First Select Function
M16C/29 Group 14.1 UARTi (i=0 to 2) • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) UiBRG count source “1” UiC1 register RE bit “0” Stop bit Start bit RxDi Sampled “L” Receive data taken in Transfer clock Reception triggered when transfer clock...
Page 205: Serial Data Logic Switching Function (Uart2)
M16C/29 Group 14.1 UARTi (i=0 to 2) 14.1.2.2. Serial Data Logic Switching Function (UART2) The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the U2RB register. Figure 14.1.2.2.1 shows serial data logic.
Page 206: Cts/Rts Separate Function (Uart0)
M16C/29 Group 14.1 UARTi (i=0 to 2) _______ _______ 14.1.2.4. CTS/RTS Separate Function (UART0) _______ _______ _______ _______ This function separates CTS /RTS , outputs RTS from the P6 pin, and accepts as input the CTS from the P6 pin. To use this function, set the register bits as shown below. _______ _______ •...
Page 207: Special Mode 1 (I 2 C Bus Mode)(Uart2)
14.1.3 Special Mode 1 (I C bus mode) (UART2) M16C/29 Group 14.1.3 Special Mode 1 (I C bus mode)(UART2) C bus mode is provided for use as a simplified I C bus interface compatible mode. Table 14.1.3.1 lists the specifications of the I C bus mode.
Page 208 14.1.3 Special Mode 1 (I C bus mode) (UART2) M16C/29 Group Start and stop condition generation block SDA2 DMA0, DMA1 request STSPSEL=1 Delay STSP circuit STSP STSPSEL=0 IICM2=1 Transmission UART2 transmit, register NACK interrupt ACKC=1 ACKC=0 request IICM=1 and UART2 IICM2=0 SDHI ACKD bit...
Page 209 14.1.3 Special Mode 1 (I C bus mode) (UART2) M16C/29 Group Table 14.1.3.2. Registers to Be Used and Settings in I C bus Mode (1) (Continued) Register Function Master Slave U2TB 0 to 7 Set transmission data Set transmission data (Note 1) U2RB 0 to 7...
Page 210 14.1.3 Special Mode 1 (I C bus mode) (UART2) M16C/29 Group Table 14.1.3.3. Registers to Be Used and Settings in I C bus Mode (2) (Continued) Register Function Master Slave U2SMR4 STAREQ Set this bit to “1” to generate start Set to “0”...
Page 211 14.1.3 Special Mode 1 (I C bus mode) (UART2) M16C/29 Group Table 14.1.3.4. I C bus Mode Functions Function Clock synchronous serial I/O C mode (SMD2 to SMD0 = 010 , IICM = 1) mode (SMD2 to SMD0 = 001 IICM2 = 0 IICM2 = 1 IICM = 0)
Page 212 14.1.3 Special Mode 1 (I C bus mode) (UART2) M16C/29 Group (1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCL2 (ACK, NACK) SDA2...
Page 213: Detection Of Start And Stop Condition
14.1.3 Special Mode 1 (I C bus mode) (UART2) M16C/29 Group 14.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDA pin changes state from high to low while the SCL pin is in the high state.
Page 214: Arbitration
14.1.3 Special Mode 1 (I C bus mode) (UART2) M16C/29 Group Table 14.1.3.2.1. STSPSEL Bit Functions Function STSPSEL = 0 STSPSEL = 1 Output of transfer clock and Output of a start/stop condition Output of SCL2 and SDA2 pins data according to the STAREQ, Output of start/stop condition is RSTAREQ and STPREQ bit...
Page 215: Transfer Clock
14.1.3 Special Mode 1 (I C bus mode) (UART2) M16C/29 Group 14.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 14.1.3.2.1. The U2SMR2 register’s CSC bit is used to synchronize the internally generated clock (internal SCL2) and an external clock supplied to the SCL pin.
Page 216: Ack And Nack
14.1.3 Special Mode 1 (I C bus mode) (UART2) M16C/29 Group 14.1.3.7 ACK and NACK If the STSPSEL bit in the U2SMR4 register is set to “0” (start and stop conditions not generated) and the ACKC bit in the U2SMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the U2SMR4 register is output from the SDA pin.
Page 217: Special Mode 2 (Uart2)
14.1.4 Special Mode 2 (UART2) M16C/29 Group 14.1.4 Special Mode 2 (UART2) Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 14.1.4.1 lists the specifications of Special Mode 2. Table 14.1.4.2 lists the registers used in Special Mode 2 and the register values set.
Page 218 14.1.4 Special Mode 2 (UART2) M16C/29 Group Microcomputer Microcomputer (Master) (Slave) Microcomputer (Slave) Figure 14.1.4.1. Serial Bus Communication Control Example (UART2) Rev.1.00 Nov 01,2004 page 198 of 402 REJ09B0101-0100Z...
Page 219 14.1.4 Special Mode 2 (UART2) M16C/29 Group Table 14.1.4.2. Registers to Be Used and Settings in Special Mode 2 Register Function U2TB(Note) 0 to 7 Set transmission data U2RB(Note) 0 to 7 Reception data can be read Overrun error flag U2BRG 0 to 7 Set a transfer rate...
Page 220: Clock Phase Setting Function
14.1.4 Special Mode 2 (UART2) M16C/29 Group 14.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the U2SMR3 register’s CKPH bit and the U2C0 register’s CKPOL bit. Make sure the transfer clock polarity and phase are the same for the master and slave to communi- cate.
Page 221 14.1.4 Special Mode 2 (UART2) M16C/29 Group "H" Slave control input "L" "H" Clock input "L" (CKPOL=0, CKPH=0) Clock input "H" (CKPOL=1, CKPH=0) "L" "H" Data output timing "L" Data input timing Indeterminate Figure 14.1.4.1.2.1. Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock) "H"...
Page 222: Special Mode 3 (Iebus Mode)(Uart2)
14.1.5 Special Mode 3 (IEBus Mode) (UART2) M16C/29 Group 14.1.5 Special Mode 3 (IEBus mode)(UART2) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform. Table 14.1.5.1 lists the registers used in IEBus mode and the register values set. Figure 14.1.5.1 shows the functions of bus collision detect function related bits.
Page 223 14.1.5 Special Mode 3 (IEBus Mode) (UART2) M16C/29 Group (1) U2SMR register ABSCS bit (bus collision detect sampling clock select) If ABSCS=0, bus collision is determined at the rising edge of the transfer clock Transfer clock TxD2 RxD2 Input to TAj Timer Aj If ABSCS=1, bus collision is determined when timer Aj (one-shot timer mode) underflows.
Page 224: Special Mode 4 (Sim Mode) (Uart2)
14.1.6 Special Mode 4 (SIM Mode) (UART2) M16C/29 Group 14.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected. Tables 14.1.6.1 lists the specifications of SIM mode.
Page 225 M16C/29 Group 14.1.6 Special Mode 4 (SIM Mode) (UART2) Table 14.1.6.2. Registers to Be Used and Settings in SIM Mode Register Function U2TB(Note) 0 to 7 Set transmission data U2RB(Note) 0 to 7 Reception data can be read OER,FER,PER,SUM Error flag U2BRG 0 to 7 Set a transfer rate...
Page 226 14.1.6 Special Mode 4 (SIM Mode) (UART2) M16C/29 Group (1) Transmission Transfer clock “1” U2C1 register TE bit Write data to U2TB register “0” “1” U2C1 register TI bit “0” Transferred from U2TB register to UART2 transmit register Parity Stop Start Parity error signal sent back from receiver...
Page 227: Parity Error Signal Output
M16C/29 Group 14.1.6 Special Mode 4 (SIM Mode) (UART2) Figure 14.1.6.2 shows the example of connecting the SIM interface. Connect T and R and apply pull-up. Microcomputer SIM card Figure 14.1.6.2. SIM Interface Connection 14.1.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2C1 register’s U2ERE bit to “1”. •...
Page 228: Format
14.1.6 Special Mode 4 (SIM Mode) (UART2) M16C/29 Group 14.1.6.2 Format • Direct Format Set the U2MR register's PRY bit to “1”, U2C0 register's UFORM bit to “0” and U2C1 register's U2LCH bit to “0”. • Inverse Format Set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”. Figure 14.1.6.2.1 shows the SIM interface format.
Page 229: O3 And Si/O4
14.2 SI/O 3 and SI/O 4 M16C/29 Group 14.2 SI/O3 and SI/O4 SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os. Figure 14.2.1 shows the block diagram of SI/O3 and SI/O4, and Figure 14.2.2 shows the SI/O3 and SI/O4- related registers. Table 14.2.1 shows the specifications of SI/O3 and SI/O4.
Page 230 14.2 SI/O 3 and SI/O 4 M16C/29 Group S I/Oi control register (i=3,4) (Note 1) Symbol Address After reset 0362 01000000 0366 01000000 Description Bit name symbol b1 b0 SMi0 Internal synchronous clock 0 0 : Selecting f or f select bit 0 1 : Selecting f 1 0 : Selecting f...
Page 231 14.2 SI/O 3 and SI/O 4 M16C/29 Group Table 14.2.1. SI/O3 and SI/O4 Specifications Item Specification Transfer data format • Transfer data length: 8 bits Transfer clock • SiC (i=3, 4) register’s SMi6 bit = “1” (internal clock) : fj/ 2(n+1) fj = f .
Page 232: Oi Operation Timing
14.2 SI/O 3 and SI/O 4 M16C/29 Group 14.2.1 SI/Oi Operation Timing Figure 14.2.1.1 shows the SI/Oi operation timing 1.5 cycle (max) (Note 3) "H" SI/Oi internal clock "L" "H" CLKi output "L" Signal written to the "H" "L" SiTRR register (Note 2) i output "H"...
Page 233: Functions For Setting An Souti Initial Value
14.2 SI/O 3 and SI/O 4 M16C/29 Group 14.2.3 Functions for Setting an S i Initial Value If the SiC register’s SMi6 bit = 0 (external clock), the S pin output can be fixed high or low when not OUTi transferring.
Page 234: A/D Converter
M16C/29 Group 15. A/D Converter 15. A/D Converter The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10 to P10 ), P0 to P0 to AN ), P1 to P1...
Page 235 M16C/29 Group 15. A/D Converter A/D conversion rate selection CKS1=1 CKS2=0 ø CKS0=1 CKS1=0 CKS0=0 CKS2=1 Resistor ladder VCUT=0 VCUT=1 Successive conversion register ADCON1 register (address 03D7 ADCON0 register (address 03D6 Addresses (03C1 to 03C0 A/D register 0(16) (03C3 to 03C2 A/D register 1(16) (03C5 to 03C4...
Page 236 M16C/29 Group 15. A/D Converter A/D control register 0 (Note) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Analog Input Pin Select Function varies with each operation mode b4 b3 A/D Operation Mode 0 0 : One-shot mode or Delayed trigger mode 0,1 Select Bit 0 0 1 : Repeat mode 1 0 : Single sweep mode or...
Page 237 M16C/29 Group 15. A/D Converter A/D trigger control register (Note 1, 2) Symbol Address After reset ADTRGCON 03D2 Bit symbol Bit name Function 0 : Other than simultaneous sample sweep A/D Operation Mode mode or delayed trigger mode 0,1 Select Bit 2 1 : Simultaneous sample sweep mode or delayed trigger mode 0,1 0 : Other than delayed trigger mode 0,1...
Page 238 M16C/29 Group 15. A/D Converter A/D conversion status register 0 (Note 1) Symbol Address After reset ADSTAT0 03D3 Bit symbol Bit name Function AN1 Trigger Status Flag 0 : AN1 trigger did not occur during ADERR0 AN0 conversion 1 : AN1 trigger occured during AN0 conversion Conversion Termination ADERR1...
Page 239 M16C/29 Group 15. A/D Converter Timer B2 special mode register (Note 1) Symbol Address After reset TB2SC 039E X0000000 Bit symbol Bit name Function Timer B2 Reload Timing 0 : Timer B2 underflow PWCON Switch Bit (Note 2) 1 : Timer A output at odd-numbered Three-Phase Output Port 0 : Three-phase output forcible cutoff IVPCR1...
Page 240: Operation Modes
M16C/29 Group 15. A/D Converter 15.1 Operation Modes 15.1.1 One-Shot Mode In one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. Table 15.1.1.1 shows the one-shot mode specifications. Figure 15.1.1.1 shows the operation example in one- shot mode.
Page 241 M16C/29 Group 15. A/D Converter A/D control register 0 (Note 1) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function b2 b1 b0 Analog Input Pin 0 0 0 : Select AN Select Bit (Note 2, 3) 0 0 1 : Select AN 0 1 0 : Select AN 0 1 1 : Select AN...
Page 242: Repeat Mode
M16C/29 Group 15. A/D Converter 15.1.2 Repeat mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 15.1.2.1 shows the repeat mode specifications. Figure 15.1.2.1 shows the operation example in repeat mode.
Page 243 M16C/29 Group 15. A/D Converter A/D control register 0 (Note 1) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function b2 b1 b0 Analog Input Pin 0 0 0 : Select AN Select Bit (Note 2, 3) 0 0 1 : Select AN 0 1 0 : Select AN 0 1 1 : Select AN...
Page 244: Single Sweep Mode
M16C/29 Group 15. A/D Converter 15.1.3 Single Sweep Mode In single sweep mode, analog voltage is applied to the selected pins are converted one-by-one to a digital code. Table 15.1.3.1 shows the single sweep mode specifications. Figure 15.1.3.1 shows the operation example in single sweep mode.
Page 245 M16C/29 Group 15. A/D Converter A/D control register 0 (Note 1) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Analog Input Pin Invalid in single sweep mode Select Bit b4 b3 A/D Operation Mode 1 0 : Single sweep mode or simultaneous Select Bit 0 sample sweep mode Trigger Select Bit...
Page 246: Repeat Sweep Mode 0
M16C/29 Group 15. A/D Converter 15.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltage is applied to the selected pins are repeatedly converted to a digital code. Table 15.1.4.1 shows the repeat sweep mode 0 specifications. Figure 15.1.4.1 shows the operation example in repeat sweep mode 0.
Page 247 M16C/29 Group 15. A/D Converter A/D control register 0 (Note 1) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Analog Input Pin Invalid in repeat sweep mode 0 Select Bit b4 b3 A/D Operation Mode 1 1 : Repeat sweep mode 0 or Select Bit 0 Repeat sweep mode 1 0 : Software trigger...
Page 248: Repeat Sweep Mode 1
M16C/29 Group 15. A/D Converter 15.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltage is applied to the all selected pins are converted to a digital code, with mainly used in the selected pins. Table 15.1.5.1 shows the repeat sweep mode 1 specifications. Figure 15.1.5.1 shows the operation example in repeat sweep mode 1.
Page 249 M16C/29 Group 15. A/D Converter A/D control register 0 (Note 1) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Analog Input Pin Invalid in repeat sweep mode 1 Select Bit b4 b3 A/D Operation Mode 1 1 : Repeat sweep mode 0 or Select Bit 0 Repeat sweep mode 1 0 : Software trigger...
Page 250: Simultaneous Sample Sweep Mode
M16C/29 Group 15. A/D Converter 15.1.6 Simultaneous Sample Sweep Mode In simultaneous sample sweep mode, analog voltage is applied to the selected pins are converted one- by-one to a digital code. At this time, the input voltage of AN0 and AN1 are sampled simultaneously using two circuits of sample and hold circuit.
Page 251 M16C/29 Group 15. A/D Converter A/D control register 0 (Note 1) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Analog Input Pin Invalid in simultaneous sample sweep mode Select Bit b4 b3 A/D Operation Mode 1 0 : Single sweep mode or simultaneous Select Bit 0 sample sweep mode Refer to Table 15.1.6.2 Trigger Select Bit...
Page 252 M16C/29 Group 15. A/D Converter A/D trigger control register (Note 1) Symbol Address After reset ADTRGCON 03D2 Bit symbol Bit name Function 1 : Simultaneous sample sweep mode A/D Operation Mode or delayed trigger mode 0, 1 Select Bit 2 A/D Operation Mode 0 : Any mode other than delayed trigger Select Bit 3...
Page 253: Delayed Trigger Mode 0
M16C/29 Group 15. A/D Converter 15.1.7 Delayed Trigger Mode 0 In delayed trigger mode 0, analog voltage is applied to the selected pins are converted one-by-one to a digital code. The delayed trigger mode 0 used in combination with A/D trigger mode of Timer B. The Timer B0 underflow starts a single sweep conversion.
Page 254 M16C/29 Group 15. A/D Converter •Example when selecting AN to AN to A/D sweep pins (SCAN1 to SCAN0="01 ") •Example 1: When Timer B1 underflow is generated during AN pin conversion A/D pin input voltage sampling Timer B0 underflow A/D pin conversion Timer B1 underflow •Example 2: When Timer B1 underflow is generated after AN pin conversion...
Page 255 M16C/29 Group 15. A/D Converter •Example when selecting AN to AN to A/D sweep pins (SCAN1 to SCAN0="01 ") •Example 1: When Timer B1 underflow is generated during AN pin conversion A/D pin input voltage sampling Timer B0 underflow A/D pin conversion Timer B1 underflow "1"...
Page 256 M16C/29 Group 15. A/D Converter •Example 3: When Timer B0 underflow is generated during A/D pin conversion of any pins except AN Timer B0 underflow Timer B0 underflow A/D pin input (Abort othrt pins conversion ) voltage sampling Timer B1 underflow Timer B1 underflow A/D pin conversion "1"...
Page 257 M16C/29 Group 15. A/D Converter A/D control register 0 (Note 1) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function b2 b1 b0 Analog Input Pin 1 1 1 : Set to "111b" in delayed trigger Select Bit mode 0 b4 b3 A/D Operation Mode...
Page 258 M16C/29 Group 15. A/D Converter A/D trigger control register (Note 1) Symbol Address After reset ADTRGCON 03D2 Bit symbol Bit name Function Simultaneous sample sweep mode or A/D Operation Mode delayed trigger mode 0,1 Select Bit 2 A/D Operation Mode Delayed trigger mode 0, 1 Select Bit 3 Refer to Table 15.1.7.2 Trigger Select...
Page 259: Delayed Trigger Mode 1
M16C/29 Group 15. A/D Converter 15.1.8 Delayed Trigger Mode 1 In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a digital code. When the input of the AD pin (falling edge) changes state from “H” to “L”, a single sweep conversion is started.
Page 260 M16C/29 Group 15. A/D Converter •Example when selecting AN to AN to A/D sweep pins (SCAN1 to SCAN0="01 ") •Example 1: When AD pin falling edge is generated during AN pin conversion A/D pin input voltage sampling A/D pin conversion pin input •Example 2: When AD pin falling edge is generated again after AN...
Page 261 M16C/29 Group 15. A/D Converter •Example when selecting AN to AN to A/D sweep pins (SCAN1 to SCAN0="01 ") •Example 1: When AD pin falling edge is generated during AN pin conversion A/D pin input voltage sampling A/D pin conversion pin input "1"...
Page 262 M16C/29 Group 15. A/D Converter •Example 3: When AD input falling edge is generated more than two times after AN pin conversion A/D pin input voltage sampling A/D pin conversion pin input (valid after single sweep conversion) (invalid) "1" ADST flag "0"...
Page 263 M16C/29 Group 15. A/D Converter A/D control register 0 (Note 1) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function b2 b1 b0 Analog Input Pin 1 1 1 : Set to "111b" in delayed trigger Select Bit mode 1 b4 b3 A/D Operation Mode...
Page 264 M16C/29 Group 15. A/D Converter A/D trigger control register (Note 1) Symbol Address After reset ADTRGCON 03D2h Bit symbol Bit name Function Simultaneous sample sweep mode or A/D Operation Mode delayed trigger mode 0,1 Select Bit 2 A/D Operation Mode Delayed trigger mode 0, 1 Select Bit 3 Refer to Table 15.1.8.2 Trigger Select...
Page 265: Resolution Select Function
M16C/29 Group 15. A/D Converter 15.2 Resolution Select Function The BITS bit in the ADCON1 register determines the resolution. When the BITS bit is set to “1” (10-bit precision), the A/D conversion result is stored into bits 0 to 9 in the ADi register (i=0 to 7). When the BITS bit is set to “0”...
Page 266: Precautions Of Using A/D Converter
M16C/29 Group 15. A/D Converter 15.6 Precautions of Using A/D Converter (1) Set the bit in the port direction register, which corresponds to the pin being used as the analog input, to “0” (input mode) Set the bit in the port direction register, which corresponds to pin AD , to “0”...
Page 267: Multi-Master I C Bus Interface
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16. Multi-master I C bus Interface The multi-master I C bus interface is a serial communication circuit based on Philips I C bus data transfer format. 2 independent channels, with both arbitration lost detection and synchronous functions, are built in for the multi-master serial communication.
Page 268 16. MULTI-MASTER I C bus INTERFACE M16C/29 Group Figure 16.1 Block diagram of multi-master I C bus interface Rev.1.00 Nov 01,2004 page 248 of 402 REJ09B0101-0100Z...
Page 269 16. MULTI-MASTER I C bus INTERFACE M16C/29 Group C0 address register Symbol Address After reset S0D0 02E2 Bit Symbol Bit Name Function Reserved bit Set to “0” Comparing with received SAD0 Slave address address data SAD1 SAD2 SAD3 SAD4 SAD5 SAD6 Figure 16.2 I C0 address register...
Page 270 16. MULTI-MASTER I C bus INTERFACE M16C/29 Group I C0 data shift register Symbol Address When reset 02E0 Function Transmit/receive data are stored. In the master transmit mode, the start condition/stop condition are triggered by writing data to the register (refer to Section 16.9 START Condition (Note 1) Generation Method and Section16.11 STOP Condition Generation Method).
Page 271 16. MULTI-MASTER I C bus INTERFACE M16C/29 Group C0 control register 0 Symbol Address After reset S1D0 02E3 Bit Symbol Bit Name Function Bit counter b2 b1 b0 0 : 8 (Number of transmit/receive 1 : 7 bits) (Note 1) 0 : 6 1 : 5 0 : 4...
Page 272 16. MULTI-MASTER I C bus INTERFACE M16C/29 Group C0 status register Symbol Address After reset 02E8 0001000X Bit Symbol Bit Name Function Last receive bit 0: Last bit = 0 (Note 1) 1: Last bit = 1 General call detecting flag 0: No general call detected ADR0 (Note 1)
Page 273 16. MULTI-MASTER I C bus INTERFACE M16C/29 Group C0 control register 1 Symbol Address When reset S3D0 02E6 00110000 Bit Symbol Bit Name Function The interrupt enable bit for 0: Disable the I C bus interface STOP condition detection interrupt of STOP condition detection 1: Enable the I C bus interface...
Page 274 16. MULTI-MASTER I C bus INTERFACE M16C/29 Group C0 control register 2 Symbol Address When reset S4D0 02E7 Bit Symbol Bit Name Function 0 : Disabled Time out detection function 1 : Enabled enable bit 0 : Not detected Time out detection flag 1 : Detected TOSEL Time out detection time...
Page 275 16. MULTI-MASTER I C bus INTERFACE M16C/29 Group C0 start/stop condition control register Symbol Address When reset S2D0 02E5 00011010 Bit Symbol Bit Name Function SSC0 START/STOP condition setting Setting for detection condition bits(Note 1) of START/STOP condition. See Table 16.2 SSC1 Recommended setting value (SSC4 - SSC0) start/stop...
Page 276: I 2 C0 Data Shift Register (S00 Register)
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.1 I C0 Data Shift Register (S00 register) The I C0 data shift register (address 02E0 ) is the 8-bit shift register to store the receive data and the write transmit data. When the transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the S clock, and each time one-bit data is output, the data of this register is shifted by one bit to the left.
Page 277: I 2 C0 Clock Control Register (S20 Register)
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.3 I C0 Clock Control Register (S20 register) The I C0 clock control register (address 02E4 ) is used to set theACK control, S mode and the S frequency. 16.3.1 Bits 0 to 4: S frequency control bits (CCR0–CCR4) These bits control the S frequency.
Page 278 16. MULTI-MASTER I C bus INTERFACE M16C/29 Group Table 16.3 Set values of I C0 clock control register and S frequency Setting value of CCR4 to CCR0 frequency (at V =4MHz, unit : kHz) (Note 1) CCR4 CCR3 CCR2 CCR1 CCR0 Standard clock mode High-speed clock mode Setting disabled...
Page 279: I 2 C0 Control Register 0 (S1D0 Register)
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.4 I C0 Control Register 0 (S1D0 register) The I C0 control register 0 (address 02E3 ) controls the data communication format. 16.4.1 Bits 0 to 2: Bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. The I C bus interface interrupt request signal is generated immediately after the number of count specified with these bits (the ACK clock is added to the number of count when the ACK clock is selected by the ACK bit (bit 7 of address...
Page 280: Bit 7: I
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.4.5 Bit 7: I C bus interface pin input level select bit (TISS) This bit selects the input level of the S and S pins of the multi-master I C bus interface. When this bit is set to “1”, the P2 and P2 become the SMBus input level.
Page 281: I 2 C0 Status Register (S10 Register)
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.5 I C0 Status Register (S10 register) The I C0 status register (address 02E8 ) controls the I C bus interface status. Use the lower-6 bit as read only if it is used for a status check. 16.5.1 Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for an ACK receive confirmation.
Page 282: Bit 4: I C Bus Interface Interrupt Request Bit (Pin)
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.5.5 Bit 4: I C bus interface interrupt request bit (PIN) This bit generates an I C bus interface interrupt request signal. After each byte data is transmitted, the PIN bit is changed from “1” to “0”. At the same time, an I C bus interface interrupt request signal is generated to the CPU.
Page 283: Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: Trx)
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.5.7 Bit 6: Communication mode select bit (transfer direction select bit: TRX) This bit decides a transfer direction for the data communication. When this bit is “0”, receive mode is selected and the data from a transmit device is received. When the bit is “1”, transmit mode is selected and the address data and the control data are output onto the S synchronized with the clock gener- ated on the S...
Page 284: I 2 C0 Control Register 1 (S3D0 Register)
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.6 I C0 control register 1 (S3D0 register) C0 control register 1 (address 02E6 ) controls I C bus interface circuit. 16.6.1 Bit 0 : Interrupt enable bit by STOP condition (SIM ) This bit enables the I C bus interface to request an I C bus interface interrupt by detecting a STOP...
Page 285: Bits 2,3 : Port Function Select Bits Ped, Pec
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group In receive mode, ACK bit = 1 WIT bit = 0 7 clock 8 clock 1 clock clock 7 bit 8 bit ACK bit 1 bit ACKBIT PIN flag Internal WAIT flag C bus interface interrupt request signal The writing signal of I...
Page 286: Bits 4,5 : Sda/Scl Logic Output Value Monitor Bits Sdam/Sclm
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.6.4 Bits 4,5 : S logic output value monitor bits S These bits enableto monitor the logic value of the S and S output signals from the I C bus interface circuit. The S bit monitors the S output logic value.
Page 287: I 2 C0 Control Register 2 (S3D0 Register)
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.7 I C0 control register 2 (S3D0 register) C0 control register 2 (address: 02E7 ) controls the abnormal communication detection. In the I C bus communication, the data transfer is controlled by the S clock signal.
Page 288: Bit0: Time Out Detection Function Enable Bit (Toe)
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.7.1 Bit0: Time out detection function enable bit (TOE) The bit enables a time out detection function. When setting this bit to “1”, the I C bus interface interrupt request signal is generated if the S clock is stopped in “H”...
Page 289: I 2 C0 Start/Stop Condition Control Registers (S2D0 Register)
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.8 I C0 START/STOP condition control registers (S2D0 register) The I C0 START/STOP condition control register(address 02E5 ) controls the detection of the START/ STOP condition. 16.8.1 Bit0-Bit4: START/STOP condition setting bits (SSC0-SSC4) Because the release time, the set up time and the hold time of the S are measured on the base of the I bus system clock(V...
Page 290: Start Condition Generation Method
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.9 START Condition Generation Method When the ES0 bit of the I C0 control register is “1” and the BB flag of the I C0 status register is “0”, writing “1” to the MST, TRX, and BB bits and “0” to the PIN and low-order bits of the I C0 status register (S10 register) simultaneously enters the standby status to generate the start condition.
Page 291: Start Condition Duplicate Protect Function
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.10 START condition duplicate protect function It is necessary to verify that the bus is not in use via the BB flag before the start condition is generated. However,when the BB flag is set to “1” because a start condition is generated by another master devices immediately after the BB flag is verified, the start condition is suspended by the start condition duplicate protect function.
Page 292 16. MULTI-MASTER I C bus INTERFACE M16C/29 Group I 2 C0 data shift register write signal Setup Hold time time Figure 16.16 Start condition generation timing diagram C0 data shift register write signal Hold Setup time time Figure 16.17 Stop condition generation timing diagram Table 16.8 Start/Stop generation timing table Item Start/Stop condition generation...
Page 293: Start/Stop Condition Detect Operation
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.12 START/STOP Condition Detect Operation Figure 16.18, Figure 16.19 and Table 16.10 show START/STOP condition detect operations. The START/ STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected only when the input signal of the S and S pins satisfied with three conditions: the S...
Page 294: Address Data Communication
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.13 Address Data Communication 16.13.1 Example of Master Transmit An example of master transmit in standard clock mode, at the S frequency of 100 kHz and in ACK return mode is shown below. 1)Set the slave address in the upper 7-bit of I C0 address registers (S0D0).
Page 295: Example Of Slave Receive
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.13.2 Example of Slave Receive An example of the slave receive in high-speed clock mode, at the S frequency of 400 kHz, in ACK return mode and using the addressing format is shown below. 1)Set a slave address in the high-order 7 bits in the I C0 address register (S0D0).
Page 296 16. MULTI-MASTER I C bus INTERFACE M16C/29 Group (1) A master transmit device transmits data to a receive device Data Data Slave address “0” 1 - 8 bits 1 - 8 bits 7 bits (2) A master receive device receives data from a transmit device Data Data Slave address...
Page 297: Usage Precautions
16. MULTI-MASTER I C bus INTERFACE M16C/29 Group 16.14 Usage precautions (1) Access to the registers of I C bus interface circuit The precaution of read/write to the control registers of I C bus interface circuit is as follows. •I C0 data shift register (S00 : 02E0 Do not write the register during the data transfer.
Page 298 16. MULTI-MASTER I C bus INTERFACE M16C/29 Group BB flag Bit reset signal Related bits 1.5V cycle Figure 16.21 The bit reset timing (The STOP condition detection) BB flag Bit reset signal Related bits BC0 - BC2 TRX(slave mode) Figure 16.22 The bit reset timing (The START condition detection) PIN bit BC0 - BC2 The bits referring...
Page 299 16. MULTI-MASTER I C bus INTERFACE M16C/29 Group (2) Generation of RESTART condition After 1-byte data transfer and a restart condition is generated, write“E0 ” to I C0 status register, set the start condition standby and the S pin will be released. Writing to the I C0 data shift register gener- ates the start condition trigger after waiting in software until the S becomes “H”.
Page 300: Can Module
M16C/29 Group 17. CAN Module 17. CAN Module The CAN (Controller Area Network) module for the M16C/29 group of microcomputers is a communication controller implementing the CAN 2.0B protocol. The M16C/29 group contains one CAN module which can transmit and receive messages in both standard (11-bit) ID and extended (29-bit) ID formats. Figure 17.1 shows a block diagram of the CAN module.
Page 301: Can Module-Related Registers
M16C/29 Group 17. CAN Module 17.1. CAN Module-Related Registers The CAN0 module has the following registers. (1) CAN Message Box A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as Basic CAN.
Page 302: Can0 Message Box
M16C/29 Group 17. CAN Module 17.1.1. CAN0 Message Box Table 17.1 shows the memory mapping of the CAN0 message box. It is possible to access to the message box in byte or word. Mapping of the message contents differs from byte access to word access. Byte access or word access can be selected by the MsgOrder bit of the C0CTLR register.
Page 303 M16C/29 Group 17. CAN Module Figures 17.2 and 17.3 show the bit mapping in each slot in byte access and word access. The content of each slot remains unchanged unless transmission or reception of a new message is performed. bit 7 bit 0 Data Byte 0 Data Byte 1...
Page 304: Acceptance Mask Registers
M16C/29 Group 17. CAN Module 17.1.2. Acceptance Mask Registers Figures 17.4 and 17.5 show the C0GMR register, the C0LMAR register, and the C0LMBR register, in which bit mapping in byte access and word access are shown. Addresses CAN0 bit 7 bit 0 0160 0161...
Page 305: Can Sfr Registers
M16C/29 Group 17. CAN Module 17.1.3. CAN SFR Registers 17.1.3.1. C0MCTLj Register (j = 0 to 15) Figure 17.6 shows the C0MCTLj register. CAN0 message control register j ( j = 0 to 15) (Note 4) Address Symbol After reset C0MCTL0 to C0MCTL15 0200 to 020F...
Page 306: C0Ctlr Register
M16C/29 Group 17. CAN Module 17.1.3.2. C0CTLR Register Figures 17.7 shows the C0CTLR register. CAN0 control register Symbol Address After reset C0CTLR 0210 X0000001 Bit symbol Bit name Function CAN module 0: Operation mode Reset reset bit (Note 1) 1: Reset/initialization mode Loop back mode 0: Normal operation mode LoopBack...
Page 307: C0Str Register
M16C/29 Group 17. CAN Module 17.1.3.3. C0STR Register Figure 17.8 shows the C0STR register. CAN0 status register (Note 1) Symbol Address After reset C0STR 0212 Bit symbol Bit name Function b3 b2 b1 b0 0 0 0 0 : Slot 0 0 0 0 1 : Slot 1 Active slot bits MBOX...
Page 308: C0Sstr Register
M16C/29 Group 17. CAN Module 17.1.3.4. C0SSTR Register Figure 17.9 shows the C0SSTR register. CAN0 slot status register (b15) (b8) b0 b7 Symbol Address After reset C0SSTR 0000 0215 , 0214 Function Setting values 0: Reception slot The message has been read. Transmission slot Slot status bits Transmission is not completed.
Page 309: C0Icr Register
M16C/29 Group 17. CAN Module 17.1.3.5. C0ICR Register Figure 17.10 shows the C0ICR register. CAN0 interrupt control register (Note) (b15) (b8) b0 b7 Symbol Address After reset C0ICR 0217 , 0216 0000 Function Setting values 0: Interrupt disabled Interrupt enable bits: 1: Interrupt enabled Each bit corresponds with a slot with the same number.
Page 310: C0Conr Register
M16C/29 Group 17. CAN Module 17.1.3.7. C0CONR Register Figure 17.12 shows the C0CONR register. CAN0 configuration register Symbol Address After reset C0CONR Indeterminate 021A Bit symbol Bit name Function Prescaler division b3 b2 b1 b0 0 0 0 0 : Divide-by-1 of f ratio select bits 0 0 0 1 : Divide-by-2 of f 0 0 1 0 : Divide-by-3 of f...
Page 311: C0Recr Register
M16C/29 Group 17. CAN Module 17.1.3.8. C0RECR Register Figure 17.13 shows the C0RECR register. CAN0 receive error count register (Note 2) Symbol Address After reset C0RECR 021C Function Counter value Reception error counting function The value is incremented or decremented to FF (Note 1) according to the CAN module’s error status.
Page 312: C0Tsr Register
M16C/29 Group 17. CAN Module 17.1.3.10. C0TSR Register Figure 17.15 shows the C0TSR register. CAN0 time stamp register (Note) (b15) (b8) b0 b7 Symbol Address After reset C0TSR 021F , 021E 0000 Function Counter value Time stamp function 0000 to FFFF Note: This register can not be set in CAN reset/initialization mode of the CAN module.
Page 313: Operational Modes
M16C/29 Group 17. CAN Module 17.2. Operational Modes The CAN module has the following four operational modes. • CAN Reset/Initialization Mode • CAN Operation Mode • CAN Sleep Mode • CAN Interface Sleep Mode Figure 17.17 shows transition between operational modes. MCU Reset Reset = 0 CAN reset/initialization...
Page 314: Can Operation Mode
M16C/29 Group 17. CAN Module 17.2.2. CAN Operation Mode The CAN operation mode is activated by setting the Reset bit in the C0CTLR register to “0”. If the Reset bit is set to “0”, check that the State_Reset bit in the C0STR register is set to “0”. If 11 consecutive recessive bits are detected after entering the CAN operation mode, the module initiates the following functions: •...
Page 315: Can Interface Sleep Mode
M16C/29 Group 17. CAN Module 17.2.4. CAN Interface Sleep Mode The CAN interface sleep mode is activated by setting the CCLK3 bit in the CCLKR register to “1”. It should never be activated but only via the CAN sleep mode. Entering the CAN interface sleep mode instantly stops the clock supply to the CPU Interface in the mod- ule and thereby reduces power dissipation.
Page 316: Configuration Of The Can Module System Clock
M16C/29 Group 17. CAN Module 17.3. Configuration of the CAN Module System Clock The M16C/29 group has a CAN module system clock select circuit. Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the BRP bit in the C0CONR register.
Page 317: Bit-Rate
M16C/29 Group 17. CAN Module 17.3.2. Bit-rate Bit-rate depends on f , the division value of the CAN module system clock, the division value of the baud rate prescaler, and the number of Tq of one bit. Table 17.2 shows the examples of bit-rate. Table 17.2 Examples of Bit-rate Bit-rate 24MHz...
Page 318: Acceptance Filtering Function And Masking Function
M16C/29 Group 17. CAN Module 17.4. Acceptance Filtering Function and Masking Function These functions serve the users to select and receive a facultative message. The C0GMR register, the C0LMAR register, and the C0LMBR register can perform masking to the standard ID and the extended ID of 29 bits.
Page 319: Acceptance Filter Support Unit (Asu)
M16C/29 Group 17. CAN Module 17.5. Acceptance Filter Support Unit (ASU) The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search. The IDs to receive are registered in the data table; a received ID is stored in the C0AFS register, and table search is performed with a decoded received ID.
Page 320: Basic Can Mode
M16C/29 Group 17. CAN Module 17.6. Basic CAN Mode When the BasicCAN bit in the C0CTLR register is set to "1", slots 14 and 15 correspond to Basic CAN mode. When slots 14 and 15 are defined as reception slots in Basic CAN mode, received messages are stored in slots 14 and 15 alternately.
Page 321: Return From Bus Off Function
M16C/29 Group 17. CAN Module 17.7. Return from Bus off Function When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by setting the RetBusOff bit in the C0CTLR register to “1” (Force return from bus off). At this time, the error state changes from bus off state to error active state.
Page 322: Reception And Transmission
M16C/29 Group 17. CAN Module 17.10. Reception and Transmission Configuration of CAN Reception and Transmission Mode Table 17.3 shows configuration of CAN reception and transmission mode. Table 17.3 Configuration of CAN Reception and Transmission Mode TrmReq RecReq Remote RspLock Communication mode of the slot Communication environment configuration mode: configure the communication mode of the slot.
Page 323: Reception
M16C/29 Group 17. CAN Module 17.10.1. Reception Figure 17.25 shows the behavior of the module when receiving two consecutive CAN messages, that fit into the slot of the shown C0MCTLj register (j = 0 to 15) and leads to losing/overwriting of the first message.
Page 324: Transmission
M16C/29 Group 17. CAN Module 17.10.2. Transmission Figure 17.26 shows the timing of the transmit sequence. TrmReq bit TrmActive bit SentData bit CAN0 Successful Transmission Interrupt TrmState bit TrmSucc bit MBOX bit Transmission slot No. j = 0 to 15 Figure 17.26 Timing of Transmit Sequence (1) If the TrmReq bit in the C0MCTLj register (j = 0 to 15) is set to “1”...
Page 325: Can Interrupt
M16C/29 Group 17. CAN Module 17.11. CAN Interrupt The CAN module provides the following CAN interrupts. • CAN0 Successful Reception Interrupt • CAN0 Successful Transmission Interrupt • CAN0 Error Interrupt Error Passive State Error BusOff State Bus Error (this feature can be disabled separately) •...
Page 326: Crc Calculation Circuit
M16C/29 Group 18. CRC Calculation Circuit 18. CRC Calculation Circuit The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X + 1) or CRC-16 (X + 1) to generate CRC code.
Page 327 M16C/29 Group 18. CRC Calculation Circuit CRC data register (b15) (b8) Symbol Address After reset b0 b7 CRCD 03BD to 03BC Indeterminate Function Setting range 0000 to FFFF CRC calculation result output CRC input register Symbol Address After reset CRCIN 03BE Indeterminate Setting range...
Page 328 M16C/29 Group 18. CRC Calculation Circuit (1) Setting 0000 (initial value) CRD data register CRCD [03BD , 03BC (2) Setting 01 CRC input register CRCIN [03BE 2 cycles After CRC calculation is complete CRD data register CRCD 1189 [03BD , 03BC Stores CRC code The code resulting from sending 01 in LSB first mode is (10000 0000).This the CRC code in the generating polynomial,...
Page 329: Programmable I/O Ports
M16C/29 Group 19. Programmable I/O Ports 19. Programmable I/O Ports The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 71 lines P0, P1,P2, P3, P6, P7, P8, P9, P10 (except P9 ) for the 80-pin version, or 55 lines P0 to P0 , P1 to P1...
Page 330: Pin Assignment Control Register (Pacr)
M16C/29 Group 19. Programmable I/O Ports 19.5 Pin Assignment Control register (PACR) Figure 19.5.1 shows the PACR. After reset PACR2 to PACR0 bit in the PACR register before you input and output if after resetting to each pin. When the PACR register isn’t set up, the input and output function of some of the pins doesn’t work.
Page 331 M16C/29 Group 19. Programmable I/O Ports Pull-up selection Direction register to P0 , P9 (inside dotted-line included) Data bus Port latch (Note 1) (inside dotted-line not included) to P3 Analog input Pull-up selection Direction register to P1 (inside dotted-line included) Port P1 control register Port latch Data bus...
Page 332 M16C/29 Group 19. Programmable I/O Ports Pull-up selection Direction register , P2 , P7 , P7 "1" Output Port latch Data bus (Note 1) Switching between CMOS and Input to respective peripheral functions Pull-up selection to P8 Direction register Port latch Data bus (Note 1) Input to respective peripheral functions...
Page 333 M16C/29 Group 19. Programmable I/O Ports Pull-up selection Direction register , P6 Data bus Port latch (Note 1) Switching between CMOS and Nch Input to respective peripheral functions Pull-up selection Direction register , P6 “1” Output Port latch Data bus (Note 1) Switching between CMOS and Nch Pull-up selection...
Page 334 M16C/29 Group 19. Programmable I/O Ports Pull-up selection to P10 (inside dotted-line Direction register not included) , P10 to P10 (inside dotted-line included) Data bus Port latch (Note 1) Analog input Input to respective peripheral functions Pull-up selection Direction register , P9 “1”...
Page 335 M16C/29 Group 19. Programmable I/O Ports Pull-up selection Direction register Data bus Port latch (Note) Pull-up selection Direction register Data bus Port latch (Note) Note: symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Figure 19.5.
Page 336 M16C/29 Group 19. Programmable I/O Ports Port Pi direction register (i=0 to 3, 6 to 8, and 10) (Note) Symbol Address After reset PD0 to PD3 03E2 , 03E3 , 03E6 , 03E7 PD6 to PD8 03EE , 03EF , 03F2 PD10 03F6 Bit symbol...
Page 337 M16C/29 Group 19. Programmable I/O Ports Port Pi register (i=0 to 3, 6 to 8 and 10) (Note) Symbol Address After reset P0 to P3 03E0 , 03E1 , 03E4 , 03E5 Indeterminate P6 to P8 03EC , 03ED , 03F0 Indeterminate 03F4 Indeterminate...
Page 338 M16C/29 Group 19. Programmable I/O Ports Pull-up control register 0 (Note) Symbol Address After reset PUR0 03FC Bit symbol Bit name Function PU00 to P0 pull-up 0 : Not pulled high PU01 to P0 pull-up 1 : Pulled high (Note) PU02 to P1 pull-up...
Page 339 M16C/29 Group 19. Programmable I/O Ports Port control register Symbpl Address After reset 03FF Bit symbol Bit name Function PCR0 Port P1 control bit Operation performed when the P1 register is read 0: When the port is set for input, the input levels of P10 to P17 pins are read.
Page 340 M16C/29 Group 19. Programmable I/O Ports NMI digital debounce register (Note) Symbol Address After reset NDDR 033E Function Setting range Assuming that set value =n, for n = 0 to FEh, NMI / SD pulse whose width is greater than (V1/8) / ( n + 1) will be input.
Page 341 M16C/29 Group 19. Programmable I/O Ports Digital Debounce Filter Clock / P1 Port In Signal Out To NMI and SD / INT5 and INPC17 Data Bus Reload Value Count Value Data Bus (write) (read) Reload Value Port In Signal Out Count Value Reload Value (continued)
Page 342 M16C/29 Group 19. Programmable I/O Ports Table 19.1. Unassigned Pin Handling in Single-chip Mode Pin name Connection After setting for input mode, connect every pin to V via a resistor(pull-down); Ports P0 to P3, or after setting for output mode, leave these pins open. (Note 1, Note 2, Note 4) P6 to P10 (Note 3) Open...
Page 343: Electrical Characteristics
M16C/29 Group 20. Electrical Characteristics (Normal-version) 20. Electrical Characteristics 20.1. Normal version Table 20.1. Absolute Maximum Ratings S y m b o l P a r a m e t e r Condition Rated value U n i t S u p p l y v o l t a g e -0.3 to 6.5 A n a l o g s u p p l y v o l t a g e -0.3 to 6.5...
Page 344 M16C/29 Group 20. Electrical Characteristics (Normal-version) Table 20.2. Recommended Operating Conditions (Note 1) Standard Symbol Parameter Unit Min. Typ. Max. Supply voltage Analog supply voltage AVcc Supply voltage AVss Analog supply voltage HIGH input to P0 , P1 to P1 , P2 to P2 , P3...
Page 345 M16C/29 Group 20. Electrical Characteristics (Normal-version) Table 20.3. A/D Conversion Characteristics (Note 1) Standard Symbol Parameter Measuring condition Unit Min. Typ. Max. Resolution Bits – ±3 Integral non- 10 bit ±5 =3.3V linearity ±2 =3.3V 8 bit error ±3 10 bit Absolute –...
Page 346 M16C/29 Group 20. Electrical Characteristics (Normal-version) Table 20.4. Flash Memory Version Electrical Characteristics (Note 1) for 100 E/W cycle products Standard Parameter Symbol Unit Min. Typ. (Note 2) Erase/Write cycle (Note 3) 100(Note 4) cycle – µs Word program time (Vcc=5.0V, Topr=25°C) –...
Page 347 M16C/29 Group 20. Electrical Characteristics (Normal-version) Table 20.6. Low Voltage Detection Circuit Electrical Characteristics (Note 1, Note 3) Standard Symbol Parameter Measuring condition Unit Max. Min. Typ. Voltage down detection voltage (Note 1) Vdet4 4.45 Vdet3 Reset level detection voltage (Notes 1) =0.8 to 5.5V Low voltage reset retention voltage (Note 2) Vdet3s...
Page 348 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 5V Table 20.8. Electrical Characteristics (Note 1) S t a n d a r d S y m b o l M e a s u r i n g c o n d i t i o n P a r a m e t e r U n i t M i n .
Page 349 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 5V Table 20.9. Electrical Characteristics (2) (Note 1) Standard Symbol Measuring condition Parameter Unit Min. Typ. Max. )=20MHz, Flash memory The output pins are open and No division other pins are V No division, On-chip oscillation 1MHz Flash memory f(BCLK)=10MHz,...
Page 350 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 20.10. External Clock Input (X input) Standard Symbol Parameter Unit...
Page 351 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 20.11. Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 352 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 20.17. Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 353 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 20.23. Multi-master I C bus Line Standard clock mode High-speed clock mode Symbol Parameter...
Page 354 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 5V c(TA) w(TAH) input w(TAL) c(UP) w(UPH) input w(UPL) input (Up/down input) During event counter mode input –UP) (When count on falling su(UP–T edge is selected) input (When count on rising edge is selected) Two-phase pulse input in event counter mode c(TA)
Page 355 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 5V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi su(D–C) d(C–Q) h(C–D) RxDi w(INL) INTi input w(INH) Figure 20.2. Timing Diagram (2) = 5V HD:STA :STO HD:STA HD:DTA HIGH :DAT :STA Figure 20.3. Timing Diagram (3) Rev.1.00 Nov 01,2004 page 335 of 402 REJ09B0101-0100Z...
Page 356 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 3V Table 20.24. Electrical Characteristics (Note 1) Standard Measuring condition S y m b o l P a r a m e t e r Unit Min. T y p . M a x . H I G H o u t p u t t o P 0 , P 1...
Page 357 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 3V Table 20.25. Electrical Characteristics (2) (Note 1) Standard Symbol Parameter Measuring condition Unit Min. Typ. Max. f(BCLK)=10MHz, Flash memory The output pins are open and No division other pins are V Flash memory f(BCLK)=10MHz, Program Vcc=3.0V...
Page 358 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 20.26. External Clock Input (X input) Standard Symbol Parameter Unit...
Page 359 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 20.27. Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 360 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 20.33. Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 361 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 20.39. Multi-master I C bus Line Standard clock mode High-speed clock mode Symbol Parameter...
Page 362 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 3V c(TA) w(TAH) input w(TAL) c(UP) w(UPH) input w(UPL) input (Up/down input) During event counter mode input –UP) (When count on falling su(UP–T edge is selected) input (When count on rising edge is selected) Two-phase pulse input in event counter mode c(TA)
Page 363 M16C/29 Group 20. Electrical Characteristics (Normal-version) = 3V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi su(D–C) d(C–Q) h(C–D) RxDi w(INL) INTi input w(INH) Figure 20.5. Timing Diagram (2) = 3V HD:STA :STO HD:STA HD:DTA HIGH :DAT :STA Figure 20.6. Timing Diagram (3) Rev.1.00 Nov 01,2004 page 343 of 402 REJ09B0101-0100Z...
Page 364: T Version
M16C/29 Group 20. Electrical Characteristics (T-version) 20.2. T version Table 20.40. Absolute Maximum Ratings S y m b o l P a r a m e t e r Condition Rated value U n i t S u p p l y v o l t a g e -0.3 to 6.5 A n a l o g s u p p l y v o l t a g e -0.3 to 6.5...
Page 365 M16C/29 Group 20. Electrical Characteristics (T-version) Table 20.41. Recommended Operating Conditions (Note 1) Standard Symbol Parameter Unit Min. Typ. Max. Supply voltage Analog supply voltage AVcc Supply voltage AVss Analog supply voltage HIGH input to P0 , P1 to P1 , P2 to P2 , P3...
Page 366 M16C/29 Group 20. Electrical Characteristics (T-version) Table 20.42. A/D Conversion Characteristics (Note 1) Standard Symbol Parameter Measuring condition Unit Typ. Max. Min. Resolution Bits – ±3 Integral non- 10 bit ±5 =3.3V linearity ±2 =3.3V 8 bit error ±3 Absolute 10 bit –...
Page 367 M16C/29 Group 20. Electrical Characteristics (T-version) Table 20.43. Flash Memory Version Electrical Characteristics (Note 1) for 100 E/W cycle products Standard Parameter Symbol Unit Min. Typ. (Note 2) Erase/Write cycle (Note 3) 100(Note 4) cycle – µs Word program time (Vcc=5.0V, Topr=25°C) –...
Page 368 M16C/29 Group 20. Electrical Characteristics (T-version) Table 20.45. Power Supply Circuit Timing Characteristics Standard Symbol Parameter Measuring condition Unit Min. Typ. Max. Time for internal power supply stabilization during powering-on td(P-R) td(ROC) Time for internal on-chip oscillator stabilization during powering-on µs td(R-S) STOP release time (Note 2)
Page 369 M16C/29 Group 20. Electrical Characteristics (T-version) = 5V Table 20.46. Electrical Characteristics (Note 1) Standard Symbol Parameter Measuring condition Unit Min. Typ. Max. HIGH output to P0 , P1 to P1 , P2 to P2 , P3 to P3 , P6 to P6 =-5mA -2.0...
Page 370 M16C/29 Group 20. Electrical Characteristics (T-version) = 5V Table 20.47. Electrical Characteristics (2) (Note 1) Standard Symbol Parameter Measuring condition Unit Min. Typ. Max. )=20MHz, Flash memory The output pins are open and No division other pins are V No division, On-chip oscillation 1MHz Flash memory f(BCLK)=10MHz,...
Page 371 M16C/29 Group 20. Electrical Characteristics (T-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 20.48. External Clock Input (X input) Standard Symbol Parameter Unit Min. Max. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width w(L)
Page 372 M16C/29 Group 20. Electrical Characteristics (T-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 20.49. Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min.
Page 373 M16C/29 Group 20. Electrical Characteristics (T-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 20.55. Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min.
Page 374 M16C/29 Group 20. Electrical Characteristics (T-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 20.61. Multi-master I C bus Line Standard clock mode High-speed clock mode Symbol Parameter Unit Min.
Page 375 M16C/29 Group 20. Electrical Characteristics (T-version) = 5V c(TA) w(TAH) input w(TAL) c(UP) w(UPH) input w(UPL) input (Up/down input) During event counter mode input –UP) (When count on falling su(UP–T edge is selected) input (When count on rising edge is selected) Two-phase pulse input in event counter mode c(TA)
Page 376 M16C/29 Group 20. Electrical Characteristics (T-version) = 5V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi su(D–C) d(C–Q) h(C–D) RxDi w(INL) INTi input w(INH) Figure 20.8. Timing Diagram (2) = 5V HD:STA :STO HD:STA HD:DTA HIGH :DAT :STA Figure 20.9. Timing Diagram (3) Rev.1.00 Nov 01,2004 page 356 of 402 REJ09B0101-0100Z...
Page 377 M16C/29 Group 20. Electrical Characteristics (T-version) = 3V Table 20.62. Electrical Characteristics (Note) Standard Measuring condition S y m b o l P a r a m e t e r Unit Min. T y p . M a x . H I G H o u t p u t t o P 0 , P 1...
Page 378 M16C/29 Group 20. Electrical Characteristics (T-version) = 3V Table 20.63. Electrical Characteristics (2) (Note 1) Standard Symbol Parameter Measuring condition Unit Min. Typ. Max. f(BCLK)=10MHz, Flash memory The output pins are open and No division other pins are V Flash memory f(BCLK)=10MHz, Program Vcc=3.0V...
Page 379 M16C/29 Group 20. Electrical Characteristics (T-version) Timing Requirements = 3V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 20.64. External Clock Input (X input) Standard Symbol Parameter Unit Min. Max. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width w(L)
Page 380 M16C/29 Group 20. Electrical Characteristics (T-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 20.65. Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min.
Page 381 M16C/29 Group 20. Electrical Characteristics (T-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 20.71. Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min.
Page 382 M16C/29 Group 20. Electrical Characteristics (T-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 20.77. Multi-master I C bus Line Standard clock mode High-speed clock mode Symbol Parameter Unit Min.
Page 383 M16C/29 Group 20. Electrical Characteristics (T-version) = 3V c(TA) w(TAH) input w(TAL) c(UP) w(UPH) input w(UPL) input (Up/down input) During event counter mode input –UP) (When count on falling su(UP–T edge is selected) input (When count on rising edge is selected) Two-phase pulse input in event counter mode c(TA)
Page 384 M16C/29 Group 20. Electrical Characteristics (T-version) = 3V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi su(D–C) d(C–Q) h(C–D) RxDi w(INL) INTi input w(INH) Figure 20.11. Timing Diagram (2) = 3V HD:STA :STO HD:STA HD:DTA HIGH :DAT :STA Figure 20.12. Timing Diagram (3) Rev.1.00 Nov 01,2004 page 364 of 402 REJ09B0101-0100Z...
Page 385: Flash Memory Version
M16C/29 Group 21. Flash Memory Version 21. Flash Memory Version 21.1 Flash Memory Performance The flash memory version is functionally the same as the mask ROM version except that it internally con- tains flash memory. In the flash memory version, the flash memory can be used in four rewrite mode : CPU rewrite mode, standard serial I/O mode, parallel I/O mode and CAN I/O.
Page 386 M16C/29 Group 21. Flash Memory Version Table 21.2. Flash Memory Rewrite Modes Overview Flash memory CPU rewrite mode Standard serial I/O Parallel I/O mode CAN I/O mode rewrite mode mode Function The user ROM area is The user ROM area The user ROM areas The user ROM areas is rewritten when the CPU is rewritten using a...
Page 387: Memory Map
M16C/29 Group 21. Flash Memory Version 21.2 Memory Map The flash memory contains the user ROM area and the boot ROM area (reserved area). Figures 21.2.1 to 21.2.3 show the flash memory block diagram. The user ROM area has space to store the microcomputer operation program in single-chip mode and a separate 4K Data block area (two 2K blocks A and B).
Page 388 M16C/29 Group 21. Flash Memory Version The M16C/29 (flash memory version) contains the flash memory that can be rewritten with a single voltage. For this flash memory, four flash memory modes area available in which to read, program, and erase: parallel I/O, standard serial I/O and CAN I/O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Pro- cessing Unit (CPU).
Page 389 M16C/29 Group 21. Flash Memory Version 00F000 Block B :2K bytes (Note 2) 00F7FF 00F800 Block A :2K bytes (Note 2) 00FFFF 0E0000 Block 5 : 32K bytes (Note 5) 0E7FFF 0E8000 Block 4 : 32K bytes (Note 5) 0EFFFF 0F0000 Block 3 : 32K bytes (Note 5) Note 1: To specify a block, use the maximum even address in the block.
Page 390: Functions To Prevent Flash Memory From Rewriting
M16C/29 Group 21. Flash Memory Version 21.3 Functions To Prevent Flash Memory from Rewriting The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code check function for standard input/output mode to prevent the flash memory from reading or rewriting. 21.3.1 ROM Code Protect Function The ROM code protect function prevents the flash memory from reading and rewriting in parallel input/ output mode.
Page 391 M16C/29 Group 21. Flash Memory Version ROM code protect control address Symbol Address Factory Setting ROMCP 0FFFFF (Note 4) Bit symbol Bit name Function Set this bit to “1” Reserved bit Set this bit to “1” Reserved bit Set this bit to “1” Reserved bit Set this bit to “1”...
Page 392: Cpu Rewrite Mode
M16C/29 Group 21. Flash Memory Version 21.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. In CPU rewrite mode, only the user ROM area shown in Figure 21.2.1 to 21.2.3 can be rewritten and the boot ROM area cannot be rewritten.
Page 393: Ew0 Mode
M16C/29 Group 21. Flash Memory Version 21.4.1 EW0 Mode The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled) and is ready to acknowledge the software commands. EW0 mode is selected by setting the FMR11 bit in the FMR1 register to “0”.
Page 394: Register Description
M16C/29 Group 21. Flash Memory Version 21.5 Register Description Figure 21.5.1 shows the flash memory control register 0 and flash memory control register 1. Figure 21.5.2 shows the flash memory control register 4. 21.5.1 Flash memory control register 0 (FMR0): •FMR 00 Bit This bit indicates the operation status of the flash memory.
Page 395: Flash Memory Control Register 1 (Fmr1)
M16C/29 Group 21. Flash Memory Version 21.5.2 Flash memory control register 1 (FMR1): •FMR11 Bit EW1 mode is entered by setting the FMR11 bit to “1” (EW1 mode). This bit is enabled only when the FMR01 bit is “1”. •FMR16 Bit The combined setting of the FMR02 bit and the FMR16 bit enables to program and erase in the user ROM area.
Page 396 M16C/29 Group 21. Flash Memory Version Flash memory control register 0 Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 FMR0 01B7 XX000001 Bit symbol Bit name Function 0: Busy (during writing or erasing) RY/BY status flag FMR00 1: Ready 0: Disables CPU rewrite mode...
Page 397 M16C/29 Group 21. Flash Memory Version Flash memory control register 4 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset FMR4 01B3 01000000 Bit name Function Bit symbol 0: Disabled Erase suspend function FMR40 1: Enabled enable bit (Note 1) FMR41 Erase suspend 0: Erase restart...
Page 398 M16C/29 Group 21. Flash Memory Version EW0 mode operation procedure Rewrite control program Set the FMR01 bit to “1” after writing “0” ( Single-chip mode CPU rewrite mode enabled) (Note 2) Set CM0, CM1, and PM1 registers (Note 1) Execute software commands Transfer a rewrite control program to internal RAM Execute the Read Array command (Note 3) area...
Page 399 M16C/29 Group 21. Flash Memory Version Low power consumption mode program Transfer a low power internal consumption mode Set the FMR01 bit to “1” after setting “0” ( program to RAM area CPU rewrite mode enabled) (Note 2) Set the FMSTP bit to “1” (flash memory stopped. Jump to the low power consumption mode Low power consumption state)(Note 1) program transferred to internal RAM area.
Page 400: Precautions In Cpu Rewrite Mode
M16C/29 Group 21. Flash Memory Version 21.6 Precautions in CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. 21.6.1 Operation Speed When CPU clock source is the main clock, before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register.
Page 401: Dma Transfer
M16C/29 Group 21. Flash Memory Version 21.6.6 DMA Transfer In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to “0”. (the auto-programming or auto-erasing duration ). 21.6.7 Writing Command and Data Write the command code and data to even addresses in the user ROM area.
Page 402: Software Commands
M16C/29 Group 21. Flash Memory Version 21.7 Software Commands Read or write 16-bit commands and data from or to even addresses in the user ROM area. When writing a command code, 8 high-order bits (D –D ) are ignored. Table 21.7.1. Software Commands First bus cycle Second bus cycle Command...
Page 403: Clear Status Register Command
M16C/29 Group 21. Flash Memory Version 21.7.3 Clear Status Register Command (50 This command clears the status register to “0”. By writing ‘xx50 ’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5 bits in the status register are set to “0”.
Page 404: Block Erase
M16C/29 Group 21. Flash Memory Version 21.7.5 Block Erase By writing ‘xx20 ’ in the first bus cycle and ‘xxD0 ’ in the second bus cycle to the highest-order (even addresse of a block) and the auto-programming/erasing (erase and erase verify) start. The FMR00 bit in the FMR0 register indicates whether the auto-programming operation has been completed.
Page 405 M16C/29 Group 21. Flash Memory Version (EW0 mode) Interrupt service routine Start (Note 3) FMR40=1 FMR41=1 Write the command code ‘xx20 ’ (Note 1) FMR46=1? Write ‘xxD0 ’ to the highest-order block address (Note 1) Access Flash Memory FMR00=1? FMR41=0 Full status check Return (Note 2,4)
Page 406: Status Register
M16C/29 Group 21. Flash Memory Version 21.8 Status Register The status register indicates the operating status of the flash memory and whether an erasing or a pro- gramming operates normally and an error ends. The FMR00, FMR06, and FMR07 bits in the FMR0 register indicate the status of the status register.
Page 407: Full Status Check
M16C/29 Group 21. Flash Memory Version 21.8.4 Full Status Check When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occur- rence of each specific error. Therefore, execution results can be verified by checking these status bits (full status check).
Page 408 M16C/29 Group 21. Flash Memory Version Full status check FMR06 =1 (1) Execute the clear status register command and set Command the status flag to “0” whether the command is FMR07=1? sequence error entered. (2) Reexecute the command after checking that it is entered correctly or the program command or the block erase command is not executed for the blocks which are protected.
Page 409: Standard Serial I/O Mode
M16C/29 Group 21. Flash Memory Version 21.9 Standard Serial I/O Mode In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial programmer which is applicable for the M16C/29 group. For more information about serial programmers, contact the manufacturer of your serial programmer.
Page 410 M16C/29 Group 21. Flash Memory Version Table 21.9.1. Pin Functions (Flash Memory Standard Serial I/O Mode) Name Description Apply the voltage guaranteed for Program and Erase to Vcc pin and 0 Power input V to Vss pin. Connect to Vcc pin. Reset input RESET Reset input pin.
Page 411 M16C/29 Group 21. Flash Memory Version BUSY SCLK M16C/29 Group (Flash memory version) Mode setup method Signal Value CNVss Reset Vss to Vcc Vcc (Note) Connect Vcc (Note) oscillator circuit Vss (Note) Package: 64P6Q-A Note: Set following either or both in serial I/O mode while the RESET pin is held L . ¥Connect the CE pin to V ¥Connect the RP pin to V and the P1...
Page 412 M16C/29 Group 21. Flash Memory Version M16C/29 Group BUSY (Flash memory version) SCLK Mode setup method Signal Value CNVss Reset Vss to Vcc Vcc (Note) Vcc (Note) Connect Vss (Note) oscillator circuit Package: 80P6Q-A Note: Set following either or both in serial I/O mode while the RESET pin is held L . ¥Connect the CE pin to V ¥Connect the RP pin to V and the P1...
Page 413: Example Of Circuit Application In Standard Serial I/O Mode
M16C/29 Group 21. Flash Memory Version 21.9.2 Example of Circuit Application in Standard Serial I/O Mode Figure 21.9.2.1 shows an example of a circuit application in standard serial I/O mode 1 and Figure 21.9.2.2 shows an example of a circuit application in standard serial I/O mode 2. Refer to the user's manual for a serial writer to handle pins controlled by the serial writer.
Page 414 M16C/29 Group 21. Flash Memory Version Microcomputer (Note 1) SCLK (CE) TxD output (Note 1) BUSY Monitor output RxD input CNVss (RP) (Note 1) (1) In this example, a selector controls the input voltage applied to CNVss to switch between single-chip mode and standard serial I/O mode. Note 1.
Page 415: Parallel I/O Mode
M16C/29 Group 21. Flash Memory Version 21.10 Parallel I/O Mode In parallel input/output mode, the user ROM can be rewritten using a parallel programmer which is appli- cable for the M16C/29 group. For more information about the parallel programmer, contact your parallel programmer manufacturer.
Page 416: Can I/O Mode
M16C/29 Group 21. Flash Memory Version 21.11 CAN I/O Mode In CAN I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a CAN programmer which is applicable for the M16C/29 group. For more information about CAN programmers, contact the manufacturer of your CAN programmer.
Page 417 M16C/29 Group 21. Flash Memory Version SCLK M16C/29 Group (Flash memory version) Mode setup method Signal Value CNVss Reset Vss to Vcc Connect Vcc (Note) oscillator Vcc (Note) Vss (Note) circuit SCLK Package: 64P6Q-A Note: Set following either or both in serial I/O mode while the RESET pin is held L . ¥Connect the CE pin to V ¥Connect the RP pin to V and the P1...
Page 418 M16C/29 Group 21. Flash Memory Version M16C/29 Group (Flash memory version) SCLK Mode setup method Signal Value CNVss Reset Vss to Vcc Vcc (Note) Connect Vcc (Note) oscillator Vss (Note) circuit SCLK Package: 80P6Q-A Note: Set following either or both in serial I/O mode while the RESET pin is held L . ¥Connect the CE pin to V ¥Connect the RP pin to V and the P1...
Page 419: Example Of Circuit Application In Can I/O Mode
M16C/29 Group 21. Flash Memory Version 21.11.2 Example of Circuit Application in CAN I/O Mode Figure 21.11.3 shows example of circuit application in CAN I/O mode. Refer to the user’s manual for CAN programmer to handle pins controlled by a CAN programmer. Microcomputer (Note 1) SCLK...
Page 420: Package
M16C/29 Group 22. Package 22. Package 64P6Q-A Recommended Plastic 64pin 10 10mm body LQFP EIAJ Package Code JEDEC Code Weight(g) Lead Material LQFP64-P-1010-0.5 – Cu Alloy Recommended Mount Pad Dimension in Millimeters Symbol – – – – 0.13 0.18 0.28 0.105 0.125 0.175...
Page 421: Register Index
M16C/29 Group Register Index Register Index DM0IC, DM1IC 67 DM0SL 85 AD0 to AD7 218 DM1SL 86 ADCON0 to ADCON2 216 DTT 121 ADIC 67 ADSTAT0 218 ADTRGCON 217 FMR0 376 AIER 79 FMR1 376 FMR4 377 BCNIC 67 BTIC 67 G1BCR0 134 G1BCR1 136 G1BT 134...
Page 422 M16C/29 Group Register Index TA2 96,122 TA21 122 P0 to P3, P6 to P10 TA2MR 95, 125 P17DDR 320 TA3 96 PACR 319 TA3MR 95 PCLKR 43 TA4 96,122 PCR 319 TA41 122 PD0 to PD3, PD6 to PD10 TA4MR 95, 125 PDRF 129 TABSR 96,110,124 PFCR 131...
Page 423 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary 0.70 Mar/ 29/Y04 “1. Overview” and “1.1. Application” are partly revised. 2, 3 Table 1.2.1 and 1.2.2 are partly revised. 8, 9 Figure 1.5.1 and 1.5.2 are partly revised. Table 1.6.1 is revised. Figure 4.8 is partly revised.
Page 424 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary “Figure 12.3.9 PFCR register and TPRC register” is deleted. Figure 12.3.1.2.1 and the section 12.3.1.2.4 are partly revised. Section “Three-phase/Port Output Switch Function” and “Figure 12.3.2.1 PFCR register and TPRC register” are added. “UART 2 special mode register 2”...
Page 425 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary Figure 21.9.1 is partly revised. Figure 21.9.2 is partly revised. Section “21.10.1 ROM Code Protect Function” is partly revised. Section “21.11.1 ROM Code Protect Function” is partly revised. Table 21.11.1 is revised. Figure 21.11.1 is revised.
Page 426 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary Table 21.1 is partly revised. Section “21.4.2 EW1 Mode” is partly revised. 0.80 Sep/03/Y04 Table 1.2.1 and Table 1.2.2 are partly revised. Table 1.4.1 to Table 1.4.3 are partly revised. Figure 1.4.1 is partly revised.
Page 427 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary “9.3 Interrupt Control” is partly revised. ______ _______ “9.6 INT Interrupt” and “9.7 NMI Interrupt” are partly revised. “9.8 Key Input Interrupt” and “9.9 CAN0 Wake-up Interrupt” are partly revised. “10.
Page 428 M16C/29 Group Hardware Manual Publication Data : Rev.0.70 Mar 29, 2004 Rev.1.00 Nov 01, 2004 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 429 M16C/29 Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...
Page 430 REJXXXXXXX-0100Z M16C/29 Group Usage Notes Reference Book RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES For the most current Usage Notes Reference Book, please visit our website. Before using this material, please visit our website to confirm that this is the most current document available.
Page 431 • The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
Page 432 Preface The “Usage Notes Reference Book” is a compilation of usage notes from the Hardware Manual as well as technical news related to this product.
Page 433 Table of Contents 1. Usage Precaution ........................ 1 1.1 Precautions for SFR ......................1 1.1.1 Precaution for 80 pin version ..................1 1.1.2 Precaution for 64 pin version ..................1 1.2 Precautions for PLL Frequency Synthesizer ..............2 1.3 Precautions for Power Control ..................3 1.4 Precautions for Protect .....................
Page 434 1.8 Precautions for Serial I/O (Clock-synchronous Serial I/O) ..........18 1.8.1 Transmission/reception .................... 18 1.8.2 Transmission ......................19 1.8.3 Reception ......................... 20 1.9 Precautions for Serial I/O (UART Mode) ................ 21 1.9.1 Special Mode 2 ....................... 21 1.9.2 Special Mode 4 (SIM Mode) ..................21 1.10 Precautions for A/D Converter ..................
Page 435 M16C/29 Group 1. Usage Precaution 1.1 Precautions for SFR 1.1.1 Precaution for 80 pin version Set the IFSR20 bit in the IFSR2A register to "0" after reset and set the PACR2 to PACR0 bits in the PACR register to "011 ".
Page 436 M16C/29 Group 1.2 Precautions for PLL Frequency Synthesizer Make the supply voltage stable to use the PLL frequency synthesizer. For ripple with the supply voltage 5V, keep below 10kHz as frequency, below 0.5V (peak to peak) as voltage fluctuation band and below 1V/mS as voltage fluctuation rate. For ripple with the supply voltage 3V, keep below 10kHz as frequency, below 0.3V (peak to peak) as voltage fluctuation band and below 0.6V/mS as voltage fluctuation rate.
Page 437 M16C/29 Group 1.3 Precautions for Power Control 1. When exiting stop mode by hardware reset, the device will startup using the on-chip oscillator. 2. Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit of CM1 register to “1”.
Page 438 M16C/29 Group 1.4 Precautions for Protect Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0” (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to “1”.
Page 439 M16C/29 Group 1.5 Precautions for Interrupts 1.5.1 Reading address 00000 Do not read the address 00000 in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 00000 during the interrupt sequence.
Page 440 M16C/29 Group 1.5.4 Changing the Interrupt Generate Factor If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0”...
Page 441 M16C/29 Group 1.5.6 Rewrite the Interrupt Control Register (1) The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register. (2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used.
Page 442 M16C/29 Group 1.5.7 Watchdog Timer Interrupt Initialize the watchdog timer after the watchdog timer interrupt occurs. Rev.1.00 Nov 01,2004 page 8 of 31 REJXXXXXXX-0100Z...
Page 443 M16C/29 Group 1.6 Precautions for DMAC 1.6.1 Write to DMAE Bit in DMiCON Register When both of the conditions below are met, follow the steps below. Conditions • The DMAE bit is set to “1” again while it remains set (DMAi is in an active state). •...
Page 444 M16C/29 Group 1.7 Precautions for Timers 1.7.1 Timer A 1.7.1.1 Timer A (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count starts).
Page 445 M16C/29 Group 1.7.1.2 Timer A (Event Counter Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
Page 446 M16C/29 Group 1.7.1.3 Timer A (One-shot Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
Page 447 M16C/29 Group 1.7.1.4 Timer A (Pulse Width Modulation Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
Page 448 M16C/29 Group 1.7.2 Timer B 1.7.2.1 Timer B (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1”...
Page 449 M16C/29 Group 1.7.2.2 Timer B (Event Counter Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1”...
Page 450 M16C/29 Group 1.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) 1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 2) register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains “0”...
Page 451 M16C/29 Group 1.7.3 Timer S 1.7.3.1 Rewrite the G1IR register When write "0" (without interrupt request) to each bit in the G1IR register, use the following instructions. Usable instructions: AND, BCLR Rev.1.00 Nov 01,2004 page 17 of 31 REJXXXXXXX-0100Z...
Page 452 M16C/29 Group 1.8 Precautions for Serial I/O (Clock-synchronous Serial I/O) 1.8.1 Transmission/reception _______ ________ 1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmission side that the ________ reception has become ready.
Page 453 M16C/29 Group 1.8.2 Transmission When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0” (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state;...
Page 454 M16C/29 Group 1.8.3 Reception 1. In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix set- tings for transmission even when using the device only for reception. Dummy data is output to the outside from the TxDi pin when receiving data. 2.
Page 455 M16C/29 Group 1.9 Precautions for Serial I/O (UART Mode) 1.9.1 Special Mode 2 _____ If a low-level signal is applied to the SD pin when the TB2SC register IVPCR1 bit = 1 (three-phase output _____ forcible cutoff by input on SD pin enabled), the RTS and CLK pins go to a high-impedance state.
Page 456 M16C/29 Group 1.10 Precautions for A/D Converter 1. Set ADCON0 (except bit 6), ADCON1, ADCON2 and ADTRGCON registers when A/D conversion is stopped (before a trigger occurs). 2. When the VCUT bit of ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref con- nected), start A/D conversion after passing 1 µs or longer.
Page 457 M16C/29 Group 8. If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi register after completion of A/D conversion, an incorrect value may be stored in the ADi register. This problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU clock.
Page 458 M16C/29 Group 1.11 Precautions for CAN Module 1.11.1 Reading C0STR Register The CAN module on the M16C/29 group updates the status of the C0STR register in a certain period. When the CPU and the CAN module access to the C0STR register at the same time, the CPU has the access priority;...
Page 459 M16C/29 Group CPU read signal Updating period of CAN module CPU reset signal C0STR register b8: State_Reset bit 0: CAN operation mode : When the CAN module’s State_Reset bit updating period matches the CPU’s read 1: CAN reset/initial- period, it does not enter reset mode, for the CPU read has the higher priority. ization mode Figure 1.11.1 When Updating Period of CAN Module Matches Access Period from CPU Wait time...
Page 460 M16C/29 Group 1.11.2 CAN Transceiver in Boot Mode When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver should be set to “high-speed mode” or “normal operation mode”. If the operation mode is controlled by the microcomputer, CAN transceiver must be set the operation mode to “high-speed mode”...
Page 461 M16C/29 Group 1.12 Precautions for Programmable I/O Ports _____ 1. If a low-level signal is applied to the SD pin when the TB2SC register IVPCR1 bit = “1” (three-phase _____ output forcible cutoff by input on SD pin enabled), the P7 to P7 , P8 and P8...
Page 462 M16C/29 Group 1.13 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc.
Page 463 M16C/29 Group 1.14 Precautions for Flash Memory Version 1.14.1 Precautions for Functions to Inhibit Rewriting Flash Memory Rewrite ID codes are stored in addresses 0FFFDF , 0FFFE3 , 0FFFEB , 0FFFEF , 0FFFF3 , 0FFFF7 and 0FFFFB . If wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial I/O mode.
Page 464 M16C/29 Group 1.14.7 Operation speed Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1 register’s CM17–6 bits. Also, set the PM1 register’s PM17 bit to 1 (with wait state).
Page 465 M16C/29 Group 1.14.11 Writing in the user ROM area EW0 Mode • If the power supply voltage drops while rewriting any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse- quently, the flash memory becomes unable to be rewritten thereafter.
Page 466 REVISION HISTORY M16C/29 GROUP USAGE NOTES Rev. Date Description Page Summary 0.70 Mar/29/Y04 Section “1.1.1 Precaution for 80 pin version” and “1.1.2 Precaution for 64 pin version” are partly revised. “10” of the section “1.10 Precautions for A-D Converter “ is added. 0.71 April/15/Y04 Section “1.3 Precautions for Power Control”...
Page 467 M16C/29 Group USAGE NOTES REFERENCE BOOK Publication Data : Rev.0.70 Mar 29, 2004 Rev.1.00 Nov 01, 2004 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 468 M16C/29 Group Usage Notes Reference Book 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...

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Renesas M16C/29 Series Hardware Manual

Processor Mode

Clock Generation Circuit

Protection

Interrupts

Watchdog Timer

Dmac

Timers

Timer S (Input Capture/Output Compare)

Serial I/O

A/D Converter

Multi-Master I C Bus Interface

CAN Module

CRC Calculation Circuit

Programmable I/O Ports

Electrical Characteristics

Flash Memory Version

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