ST STM32G4 Series Reference Manual page 1015

Advanced arm-based 32-bit mcus

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Bit 7 FLT1LCK: Fault 1 lock

Refer to FLT5LCK description in HRTIM_FLTINR2 register.

Bits 6:3 FLT1F[3:0]: Fault 1 filter

Refer to FLT5F[3:0] description in HRTIM_FLTINR2 register.

Bit 2 FLT1SRC[0]: Fault 1 source bit 0

Refer to FLT5SRC[0] description in HRTIM_FLTINR2 register.

Bit 1 FLT1P: Fault 1 polarity

Refer to FLT5P description in HRTIM_FLTINR2 register.

Bit 0 FLT1E: Fault 1 enable

Refer to FLT5E description in HRTIM_FLTINR2 register.

RM0440 Rev 1

High-resolution timer (HRTIM)

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