ST STM32G4 Series Reference Manual page 1367

RM0440
Bit 16 DTAE: Deadtime asymmetric enable
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 DTGF[7:0]: Dead-time falling edge generator setup
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
29.7.18 TIM15 input selection register (TIM15_TISEL)
Address offset: 0x5C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:8 TI2SEL[3:0]: selects tim_ti2_in[0..15] input
0000: TIM15_CH2 input (tim_ti2_in0)
0001: tim_ti2_in0
...
0100: tim_ti2_in15
Refer to
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 TI1SEL[3:0]: selects tim_ti1_in[0..15] input
0000: TIM15_CH1 input (tim_ti1_in0)
0001: tim_ti1_in0
...
1111: tim_ti1_in15
Refer to
0: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register
1: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is
defined with DTGF[7:0] bits.
(LOCK bits in TIM15_BDTR register).
This bit-field defines the duration of the dead-time inserted between the complementary
outputs, on the falling edge.
DTGF[7:5]=0xx => DTF=DTGF[7:0]x t
DTGF[7:5]=10x => DTF=(64+DTGF[5:0])xt
DTGF[7:5]=110 => DTF=(32+DTGF[4:0])xt
DTGF[7:5]=111 => DTF=(32+DTGF[4:0])xt
Example if T =125ns (8MHz), dead-time possible values are:
DTS
0 to 15875 ns by 125 ns steps,
16 us to 31750 ns by 250 ns steps,
32 us to 63us by 1 us steps,
64 us to 126 us by 2 us steps
(LOCK bits in TIM15_BDTR register).
28 27 26 25
Res. Res. Res.
12 11 10 9
TI2SEL[3:0]
rw rw rw
Section 29.4.2: TIM15/TIM16/TIM17 pins and internal signals
Section 29.4.2: TIM15/TIM16/TIM17 pins and internal signals
General-purpose timers (TIM15/TIM16/TIM17)
with t =t
dtg dtg
with T
dtg
with T
dtg
with T
dtg
24 23 22
Res. Res. Res.
8 7 6
Res. Res.
rw
RM0440 Rev 1
.
DTS
=2xt .
dtg DTS
=8xt .
dtg DTS
=16xt .
dtg DTS
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. TI1SEL[3:0]
rw rw
for interconnects list.
for interconnects list.
17 16
Res. Res.
1 0
rw rw
1367/2083
1399