ST STM32G4 Series Reference Manual page 1396

Advanced arm-based 32-bit mcus

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General-purpose timers (TIM15/TIM16/TIM17)

TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17)

Address offset: 0x064

Reset value: 0x0000 0001

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:16 OCRSEL[2:0]: tim_ocref_clr source selection

Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK

Bits 15:0 Reserved, must be kept at reset value.

TIMx DMA control register (TIMx_DCR)(x = 16 to 17)

Address offset: 0x3DC

Reset value: 0x0000 0000

These bits select the tim_ocref_clr input source.

000: tim_ocref_clr0

001: tim_ocref_clr1

010: tim_ocref_clr2

011: tim_ocref_clr3

100: tim_ocref_clr4

101: tim_ocref_clr5

110: tim_ocref_clr6

111: tim_ocref_clr7

Section 29.4.2: TIM15/TIM16/TIM17 pins and internal signals

implementation.

bits in TIMx_BDTR register).

RM0440 Rev 1

for product specific

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