ST STM32G4 Series Reference Manual page 1270

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Bit 2 CC2IF: Capture/Compare 2 interrupt flag
Refer to CC1IF description
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output: This flag is set by hardware when the counter
matches the compare value, with some exception in center-aligned mode (refer to the CMS
bits in the TIMx_CR1 register description) and in retriggerable one pulse mode. It is cleared
by software.
0: No match.
1: The content of the counter TIMx_CNT has matched the content of the TIMx_CCR1
register.
If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared
by software or by reading the TIMx_CCR1 register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected
on tim_ic1 which matches the selected polarity).
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
At overflow or underflow and if UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and
UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by a trigger event (refer to the synchro control register description),
if URS=0 and UDIS=0 in the TIMx_CR1 register.
28.5.6 TIMx event generation register (TIMx_EGR)(x = 2 to 5)
Address offset: 0x014
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:7 Reserved, must be kept at reset value.
Bit 6 TG: Trigger generation
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4G: Capture/compare 4 generation
Bit 3 CC3G: Capture/compare 3 generation
1270/2083
12 11 10 9
Res. Res. Res.
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Refer to CC1G description
Refer to CC1G description
8 7 6
Res. Res. TG
w
RM0440 Rev 1
5 4 3 2
Res. CC4G CC3G CC2G
w w w
RM0440
1 0
CC1G UG
w w