ST STM32G4 Series Reference Manual page 1016

High-resolution timer (HRTIM)
26.5.72 HRTIM fault input register 2 (HRTIM_FLTINR2)
Address offset: 0x3D4
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
FLT6
FLT6F[3:0]
LCK
rwo rw rw
Bits 31:26 Reserved, must be kept at reset value.
Bits 25:24 FLTSD[1:0]: Fault sampling clock division
This bitfield indicates the division ratio between the timer clock frequency (f
signal sampling clock (f
00: f
FLTS
01: f
FLTS
10: f
FLTS
11: f
FLTS
Note: This bitfield must be written prior to any of the FLTxE enable bits.
Bits 23:21 Reserved, must be kept at reset value.
Bit 21 FLT6SRC[1]: Fault 6 source bit 1
Refer to FLT5SRC[0] description.
Bit 20 FLT5SRC[1]: Fault 5 source bit 1
Refer to FLT5SRC[0] description.
Bit 19 FLT4SRC[1]: Fault 4 source bit 1
Refer to FLT5SRC[0] description.
Bit 18 FLT3SRC[1]: Fault 3 source bit 1
Refer to FLT5SRC[0] description.
Bit 17 FLT2SRC[1]: Fault 2 source bit 1
Refer to FLT5SRC[0] description.
Bit 16 FLT1SRC[1]: Fault 1 source bit 1
Refer to FLT5SRC[0] description.
Bit 15 FLT6LCK: Fault 6 lock
Refer to FLT5LCK description.
Bits 14:11 FLT6F[3:0]: Fault 6 filter
Refer to FLT5F[3:0] description.
Bit 10 FLT6SRC[0]: Fault 6 source bit 0
Refer to FLT5SRC[0] description.
Bit 9 FLT6P: Fault 6 polarity
Refer to FLT5P description.
1016/2083
28 27 26 25
Res. Res. FLTSD[1:0]
rw
12 11 10 9
FLT6
FLT6P
SRC[0]
rw rw rw rw
) used by the digital filters.
FLTS
=f
HRTIM
=f / 2
HRTIM
=f / 4
HRTIM
=f / 8
HRTIM
24 23 22
FLT6
Res. Res.
SRC[1]
rw
8 7 6
FLT5
FLT6E
LCK
rw rwo rw
RM0440 Rev 1
21 20 19 18
FLT5 FLT4 FLT3
SRC[1] SRC[1] SRC[1]
rw rw rw rw
5 4 3 2
FLT5
FLT5F[3:0]
SRC[0]
rw rw rw rw
) and the fault
HRTIM
RM0440
17 16
FLT2 FLT1
SRC[1] SRC[1]
rw rw
1 0
FLT5P FLT5E
rw rw