ST STM32G4 Series Reference Manual page 1370

General-purpose timers (TIM15/TIM16/TIM17)
Bit 2 BKCMP2E: tim_brk_cmp2 enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 1 BKCMP1E: tim_brk_cmp1 enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 0 BKINE: TIMx_BKIN input enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
29.7.20 TIM15 alternate function register 2 (TIM15_AF2)
Address offset: 0x064
Reset value: 0x0000 0001
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:16 OCRSEL[2:0]: ocref_clr source selection
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
1370/2083
This bit enables the tim_brk_cmp2 for the timer's tim_brk input. tim_brk_cmp2 output is
'ORed' with the other tim_brk sources.
0: tim_brk_cmp2 input disabled
1: tim_brk_cmp2 input enabled
in TIM15_BDTR register).
This bit enables the tim_brk_cmp1 for the timer's tim_brk input. tim_brk_cmp1 output is
'ORed' with the other tim_brk sources.
0: tim_brk_cmp1 input disabled
1: tim_brk_cmp1 input enabled
in TIM15_BDTR register).
This bit enables the TIMx_BKIN alternate function input for the timer's tim_brk input.
TIMx_BKIN input is 'ORed' with the other tim_brk sources.
0: TIMx_BKIN input disabled
1: TIMx_BKIN input enabled
in TIM15_BDTR register).
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
These bits select the ocref_clr input source.
000: tim_ocref_clr0
001: tim_ocref_clr1
010: tim_ocref_clr2
011: tim_ocref_clr3
100: tim_ocref_clr4
101: tim_ocref_clr5
110: tim_ocref_clr6
111: tim_ocref_clr7
Refer to Section 29.4.2: TIM15/TIM16/TIM17 pins and internal signals
implementation.
bits in TIM15_BDTR register).
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0440 Rev 1
21 20 19 18
Res. Res. Res.
rw
5 4 3 2
Res. Res. Res. Res.
for product specific
RM0440
17 16
OCRSEL[2:0]
rw rw
1 0
Res. Res.