ST STM32G4 Series Reference Manual page 1004

High-resolution timer (HRTIM)
Bit 8 EE2POL: External event 2 polarity
Refer to EE1POL description.
Bits 7:6 EE2SRC[1:0]: External event 2 source
Refer to EE1SRC[1:0] description.
Bit 5 EE1FAST: External event 1 fast mode
0: External event 1 is re-synchronized by the HRTIM logic before acting on outputs, which adds a
f clock-related latency
HRTIM
1: External event 1 is acting asynchronously on outputs (low latency mode)
Note: This bit must not be modified once the counter in which the event is used is enabled (TxCEN bit
set).
Bits 4:3 EE1SNS[1:0]: External event 1 sensitivity
00: On active level defined by EE1POL bit
01: Rising edge, whatever EE1POL bit value
10: Falling edge, whatever EE1POL bit value
11: Both edges, whatever EE1POL bit value
Bit 2 EE1POL: External event 1 polarity
This bit is only significant if EE1SNS[1:0] = 00.
0: External event is active high
1: External event is active low
Note: This parameter cannot be changed once the timer x is enabled. It must be configured prior to
setting EE1FAST bit.
Bits 1:0 EE1SRC[1:0]: External event 1 source
This bitfield selects the External event 1 source. See
00: hrtim_eev1_1
01: hrtim_eev1_2
10: hrtim_eev1_3
11: hrtim_eev1_4
Note: This parameter cannot be changed once the timer x is enabled. It must be configured prior to
setting EE1FAST bit.
1004/2083
Table 201
RM0440 Rev 1
for details.
RM0440