ST STM32G4 Series Reference Manual page 1133

RM0440
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 MMS[3]: Master mode selection - bit 3
Bit 24 Reserved, must be kept at reset value.
Bits 23:20 MMS2[3:0]: Master mode selection 2
These bits allow the information to be sent to ADC for synchronization (tim_trgo2) to be
selected. The combination is as follows:
0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo2). If
the reset is generated by the trigger input (slave mode controller configured in reset mode),
the signal on tim_trgo2 is delayed compared to the actual reset.
0001: Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo2). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enabled. The Counter Enable signal is generated by a logic AND between the CEN control
bit and the trigger input when configured in Gated mode. When the Counter Enable signal is
controlled by the trigger input, there is a delay on tim_trgo2, except if the Master/Slave mode
is selected (see the MSM bit description in TIMx_SMCR register).
0010: Update - the update event is selected as trigger output (tim_trgo2). For instance, a
master timer can then be used as a prescaler for a slave timer.
0011: Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to
be set (even if it was already high), as soon as a capture or compare match occurs
(tim_trgo2).
0100: Compare - tim_oc1ref signal is used as trigger output (tim_trgo2)
0101: Compare - tim_oc2ref signal is used as trigger output (tim_trgo2)
0110: Compare - tim_oc3ref signal is used as trigger output (tim_trgo2)
0111: Compare - tim_oc4ref signal is used as trigger output (tim_trgo2)
1000: Compare - tim_oc5ref signal is used as trigger output (tim_trgo2)
1001: Compare - tim_oc6ref signal is used as trigger output (tim_trgo2)
1010: Compare Pulse - tim_oc4ref rising or falling edges generate pulses on tim_trgo2
1011: Compare Pulse - tim_oc6ref rising or falling edges generate pulses on tim_trgo2
1100: Compare Pulse - tim_oc4ref or tim_oc6ref rising edges generate pulses on tim_trgo2
1101: Compare Pulse - tim_oc4ref rising or tim_oc6ref falling edges generate pulses on
tim_trgo2
1110: Compare Pulse - tim_oc5ref or tim_oc6ref rising edges generate pulses on tim_trgo2
1111: Compare Pulse - tim_oc5ref rising or tim_oc6ref falling edges generate pulses on
tim_trgo2
Note: The clock of the slave timer or ADC must be enabled prior to receive events from the
Bit 19 Reserved, must be kept at reset value.
Bit 18 OIS6: Output idle state 6 (tim_oc6 output)
Refer to OIS1 bit
Bit 17 Reserved, must be kept at reset value.
Bit 16 OIS5: Output idle state 5 (tim_oc5 output)
Refer to OIS1 bit
Bit 15 OIS4N: Output idle state 4 (tim_oc4n output)
Refer to OIS1N bit
Bit 14 OIS4: Output idle state 4 (tim_oc4 output)
Refer to OIS1 bit
Bit 13 OIS3N: Output idle state 3 (tim_oc3n output)
Refer to OIS1N bit
master timer, and must not be changed on-the-fly while triggers are received from the
master timer.
RM0440 Rev 1
Advanced-control timers (TIM1/TIM8/TIM20)
1133/2083
1181