ST STM32G4 Series Reference Manual page 1292

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:14 ETRSEL[3:0]: etr_in source selection
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
Bits 13:0 Reserved, must be kept at reset value.
28.5.28 TIMx alternate function register 2 (TIMx_AF2)(x = 2 to 5)
Address offset: 0x064
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:15 OCRSEL[2:0]: ocref_clr source selection
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
Bits 15:0 Reserved, must be kept at reset value.
1292/2083
These bits select the etr_in input source.
0000: tim_etr0: TIMx_ETR input
0001: tim_etr1
...
1111: tim_etr15
Refer to Section 28.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals
implementation.
bits in TIMx_BDTR register).
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
These bits select the ocref_clr input source.
000: tim_ocref_clr0
001: tim_ocref_clr1
...
111: tim_ocref_clr7
Refer to Section 28.4.2: TIM2/TIM3/TIM4/TIM5 pins and internal signals
implementation.
bits in TIMx_BDTR register).
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0440 Rev 1
for product specific
21 20 19 18
Res. Res. Res.
rw
5 4 3 2
Res. Res. Res. Res.
for product specific
RM0440
17 16
OCRSEL[2:0]
rw rw
1 0
Res. Res.