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STM32G0 1 Series
ST STM32G0 1 Series Manuals
Manuals and User Guides for ST STM32G0 1 Series. We have
1
ST STM32G0 1 Series manual available for free PDF download: Reference Manual
ST STM32G0 1 Series Reference Manual (1390 pages)
Brand:
ST
| Category:
Microcontrollers
| Size: 17.44 MB
Table of Contents
Table of Contents
2
Peripherals Independent Clock Configuration Register
2
Documentation Conventions
53
General Information
53
List of Abbreviations for Registers
53
Glossary
54
Availability of Peripherals
54
Table 1. Peripherals Versus Products
54
Memory and Bus Architecture
56
System Architecture
56
Figure 1. System Architecture
56
Memory Organization
58
Introduction
58
Memory Map and Register Boundary Addresses
59
Figure 2. Memory Map
59
Table 2. Stm32G0B1Xx and Stm32G0C1Xx Memory Boundary Addresses
60
Table 3. Stm32G071Xx and Stm32G081Xx Memory Boundary Addresses
60
Table 4. Stm32G051Xx and Stm32G061Xx Memory Boundary Addresses
60
Table 5. Stm32G031Xx and Stm32G041Xx Memory Boundary Addresses
61
Table 6. Stm32G0X1 Peripheral Register Boundary Addresses
62
Embedded SRAM
64
Table 7. SRAM Size
64
Flash Memory Overview
65
Boot Configuration
65
Table 8. Boot Modes
65
Embedded Flash Memory (FLASH)
68
FLASH Introduction
68
FLASH Main Features
68
FLASH Functional Description
69
FLASH Memory Organization
69
Table 9. Flash Memory Organization for Single-Bank Devices
69
Table 10. Flash Memory Organization for 256 Kbytes Dual-Bank Devices
70
FLASH Empty Check
71
FLASH Error Code Correction (ECC)
71
Table 11. Flash Memory Organization for 512 Kbytes Dual-Bank Devices
71
FLASH Read Access Latency
72
Table 12. Number of Wait States According to Flash Memory Clock (HCLK) Frequency
72
FLASH Memory Acceleration
73
FLASH Program and Erase Operations
74
FLASH Main Memory Erase Sequences
74
Table 13. Page Erase Overview
75
Table 14. Mass Erase Overview
75
FLASH Main Memory Programming Sequences
76
Read-While-Write (RWW) Function
79
FLASH Option Bytes
80
FLASH Option Byte Description
80
Table 15. Option Byte Format
80
Table 16. Organization of Option Bytes
81
FLASH Option Byte Programming
89
FLASH Memory Protection
91
FLASH Read Protection (RDP)
91
Table 17. Flash Memory Read Protection Status
92
FLASH Proprietary Code Readout Protection (PCROP)
94
Table 19. Access Status Versus Protection Level and Execution Modes
94
Figure 3. Changing Read Protection (RDP) Level
94
FLASH Write Protection (WRP)
96
Securable Memory Area
97
Disabling Core Debug Access
98
Forcing Boot from Flash Memory
98
FLASH Interrupts
98
Table 22. Securable Memory Erase at RDP Level 1 to Level 0 Change
98
Figure 4. Example of Disabling Core Debug Access
98
Table 23. FLASH Interrupt Requests
99
FLASH Registers
100
FLASH Access Control Register (FLASH_ACR)
100
FLASH Key Register (FLASH_KEYR)
101
FLASH Option Key Register (FLASH_OPTKEYR)
101
FLASH Status Register (FLASH_SR)
102
FLASH Control Register (FLASH_CR)
104
FLASH ECC Register (FLASH_ECCR)
106
FLASH ECC Register 2 (FLASH_ECCR2)
107
FLASH Option Register (FLASH_OPTR)
108
Table 10
108
FLASH PCROP Area a Start Address Register (FLASH_PCROP1ASR)
110
FLASH PCROP Area a End Address Register (FLASH_PCROP1AER)
110
FLASH WRP Area a Address Register (FLASH_WRP1AR)
111
FLASH WRP Area B Address Register (FLASH_WRP1BR)
112
FLASH PCROP Area B Start Address Register (FLASH_PCROP1BSR)
112
FLASH PCROP Area B End Address Register (FLASH_PCROP1BER)
113
FLASH PCROP2 Area a Start Address Register (FLASH_PCROP2ASR)
113
FLASH PCROP2 Area a End Address Register (FLASH_PCROP2AER)
114
FLASH WRP2 Area a Address Register (FLASH_WRP2AR)
114
FLASH WRP2 Area B Address Register (FLASH_WRP2BR)
115
FLASH PCROP2 Area B Start Address Register (FLASH_PCROP2BSR)
115
FLASH PCROP2 Area B End Address Register (FLASH_PCROP2BER)
116
FLASH Security Register (FLASH_SECR)
116
FLASH Register Map
117
Table 24. FLASH Register Map and Reset Values
117
Power Control (PWR)
119
Power Supplies
119
ADC and DAC Reference Voltage
120
Battery Backup of RTC Domain
120
Figure 5. Power Supply Overview
120
Voltage Regulator
122
Dynamic Voltage Scaling Management
123
Power Supply Supervisor
124
Power-On Reset (POR) / Power-Down Reset (PDR) / Brown-Out Reset
124
(Bor)
124
Figure 6. POR, PDR, and BOR Thresholds
124
Programmable Voltage Detector (PVD)
125
Figure 7. PVD Thresholds
125
Low-Power Modes
126
Figure 8. Low-Power Modes State Diagram
127
Table 25. Low-Power Mode Summary
128
Table 26. Functionalities Depending on the Working Mode
129
Run Mode
131
Low-Power Run Mode (LP Run)
131
Low-Power Modes
132
Table 27. Low-Power Run
132
Sleep Mode
133
Table 28. Sleep Mode Summary
133
Low-Power Sleep Mode (LP Sleep)
134
Stop 0 Mode
135
Table 29. Low-Power Sleep Mode Summary
135
Table 30. Stop 0 Mode Summary
137
Stop 1 Mode
138
Table 31. Stop 1 Mode Summary
138
Standby Mode
139
Table 32. Standby Mode Summary
140
Shutdown Mode
141
Auto-Wakeup from Low-Power Mode
142
Table 33. Shutdown Mode Summary
142
PWR Registers
143
Power Control Register 1 (PWR_CR1)
143
Power Control Register 2 (PWR_CR2)
144
Power Control Register 3 (PWR_CR3)
146
Power Control Register 4 (PWR_CR4)
147
Power Status Register 1 (PWR_SR1)
148
Power Status Register 2 (PWR_SR2)
149
Power Status Clear Register (PWR_SCR)
151
Power Port a Pull-Up Control Register (PWR_PUCRA)
151
Power Port a Pull-Down Control Register (PWR_PDCRA)
152
Power Port B Pull-Up Control Register (PWR_PUCRB)
152
Power Port B Pull-Down Control Register (PWR_PDCRB)
153
Power Port C Pull-Up Control Register (PWR_PUCRC)
153
Power Port C Pull-Down Control Register (PWR_PDCRC)
154
Power Port D Pull-Up Control Register (PWR_PUCRD)
154
Power Port D Pull-Down Control Register (PWR_PDCRD)
155
Power Port E Pull-Up Control Register (PWR_PUCRE)
155
Power Port E Pull-Down Control Register (PWR_PDCRE)
156
Power Port F Pull-Up Control Register (PWR_PUCRF)
156
Power Port F Pull-Down Control Register (PWR_PDCRF)
157
PWR Register Map
158
Table 34. PWR Register Map and Reset Values
158
Reset and Clock Control (RCC)
160
Reset
160
Power Reset
160
System Reset
160
Figure 9. Simplified Diagram of the Reset Circuit
161
RTC Domain Reset
162
Clocks
163
Figure 10. Clock Tree
166
HSE Clock
167
Figure 11. HSE/ LSE Clock Sources
167
HSI16 Clock
168
HSI48 Clock
169
Pll
169
LSE Clock
170
LSI Clock
170
System Clock (SYSCLK) Selection
171
Clock Source Frequency Versus Voltage Scaling
171
Clock Security System (CSS)
171
Table 35. Clock Source Frequency
171
Clock Security System for LSE Clock (LSECSS)
172
ADC Clock
172
RTC Clock
172
Timer Clock
173
Watchdog Clock
173
Clock-Out Capability
173
Internal/External Clock Measurement with TIM14/TIM16/TIM17
174
Figure 12. Frequency Measurement with TIM14 in Capture Mode
174
Figure 13. Frequency Measurement with TIM16 in Capture Mode
175
Figure 14. Frequency Measurement with TIM17 in Capture Mode
175
Peripheral Clock Enable Registers
176
Low-Power Modes
177
RCC Registers
178
Clock Control Register (RCC_CR)
178
Internal Clock Source Calibration Register (RCC_ICSCR)
180
Clock Configuration Register (RCC_CFGR)
180
PLL Configuration Register (RCC_PLLCFGR)
183
RCC Clock Recovery RC Register (RCC_CRRCR)
186
Clock Interrupt Enable Register (RCC_CIER)
186
Clock Interrupt Flag Register (RCC_CIFR)
187
Clock Interrupt Clear Register (RCC_CICR)
189
I/O Port Reset Register (RCC_IOPRSTR)
190
AHB Peripheral Reset Register (RCC_AHBRSTR)
190
APB Peripheral Reset Register 1 (RCC_APBRSTR1)
191
APB Peripheral Reset Register 2 (RCC_APBRSTR2)
194
I/O Port Clock Enable Register (RCC_IOPENR)
196
AHB Peripheral Clock Enable Register (RCC_AHBENR)
197
APB Peripheral Clock Enable Register 1 (RCC_APBENR1)
198
APB Peripheral Clock Enable Register 2(RCC_APBENR2)
201
I/O Port in Sleep Mode Clock Enable Register (RCC_IOPSMENR)
202
AHB Peripheral Clock Enable in Sleep/Stop Mode Register (RCC_AHBSMENR)
203
APB Peripheral Clock Enable in Sleep/Stop Mode Register 1
205
(Rcc_Apbsmenr1)
205
APB Peripheral Clock Enable in Sleep/Stop Mode Register 2
208
(Rcc_Apbsmenr2)
208
Peripherals Independent Clock Configuration Register (RCC_CCIPR)
209
(Rcc_Ccipr2)
212
RTC Domain Control Register (RCC_BDCR)
213
Control/Status Register (RCC_CSR)
215
RCC Register Map
217
Table 36. RCC Register Map and Reset Values
217
Clock Recovery System (CRS)
221
Introduction
221
CRS Main Features
221
CRS Implementation
221
Table 37. CRS Features
221
CRS Functional Description
222
CRS Block Diagram
222
Synchronization Input
222
Table 38. CRS Internal Input/Output Signals
222
Figure 15. CRS Block Diagram
222
Frequency Error Measurement
223
Figure 16. CRS Counter Behavior
223
Frequency Error Evaluation and Automatic Trimming
224
CRS Initialization and Configuration
224
CRS Low-Power Modes
225
CRS Interrupts
225
Table 39. Effect of Low-Power Modes on CRS
225
Table 40. Interrupt Control Bits
225
CRS Registers
226
CRS Control Register (CRS_CR)
226
CRS Configuration Register (CRS_CFGR)
227
CRS Interrupt and Status Register (CRS_ISR)
228
CRS Interrupt Flag Clear Register (CRS_ICR)
230
CRS Register Map
231
Table 41. CRS Register Map and Reset Values
231
General-Purpose I/Os (GPIO)
232
Introduction
232
GPIO Main Features
232
GPIO Functional Description
232
Table 42. Port Bit Configuration Table
233
Figure 17. Basic Structure of an I/O Port Bit
233
General-Purpose I/O (GPIO)
234
I/O Pin Alternate Function Multiplexer and Mapping
234
I/O Port Control Registers
235
I/O Port Data Registers
235
I/O Data Bitwise Handling
236
GPIO Locking Mechanism
236
I/O Alternate Function Input/Output
236
External Interrupt/Wakeup Lines
237
Input Configuration
237
Figure 18. Input Floating/Pull Up/Pull down Configurations
237
Output Configuration
238
Alternate Function Configuration
238
Figure 19. Output Configuration
238
Analog Configuration
239
Figure 20. Alternate Function Configuration
239
Figure 21. High Impedance-Analog Configuration
239
Using the HSE or LSE Oscillator Pins as Gpios
240
Using the GPIO Pins in the RTC Domain
240
USB PD / Dead Battery Support
240
GPIO Registers
241
GPIO Port Mode Register (Gpiox_Moder)
241
(X =A to F)
241
GPIO Port Output Type Register (Gpiox_Otyper)
241
GPIO Port Output Speed Register (Gpiox_Ospeedr)
242
(X = a to F)
242
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupdr)
242
GPIO Port Input Data Register (Gpiox_Idr)
243
(X = a to F)
243
GPIO Port Output Data Register (Gpiox_Odr)
243
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr)
243
GPIO Port Configuration Lock Register (Gpiox_Lckr)
244
(X = a to F)
244
(X = a to F)
245
(X = a to F)
246
GPIO Port Bit Reset Register (Gpiox_Brr) (X = a to F)
246
GPIO Register Map
247
Table 43. GPIO Register Map and Reset Values
247
System Configuration Controller (SYSCFG)
248
SYSCFG Registers
248
SYSCFG Configuration Register 1 (SYSCFG_CFGR1)
248
SYSCFG Configuration Register 2 (SYSCFG_CFGR2)
251
SYSCFG Interrupt Line 0 Status Register (SYSCFG_ITLINE0)
253
SYSCFG Interrupt Line 1 Status Register (SYSCFG_ITLINE1)
254
SYSCFG Interrupt Line 2 Status Register (SYSCFG_ITLINE2)
254
SYSCFG Interrupt Line 3 Status Register (SYSCFG_ITLINE3)
254
SYSCFG Interrupt Line 4 Status Register (SYSCFG_ITLINE4)
255
SYSCFG Interrupt Line 5 Status Register (SYSCFG_ITLINE5)
256
SYSCFG Interrupt Line 6 Status Register (SYSCFG_ITLINE6)
256
SYSCFG Interrupt Line 7 Status Register (SYSCFG_ITLINE7)
256
SYSCFG Interrupt Line 8 Status Register (SYSCFG_ITLINE8)
257
SYSCFG Interrupt Line 9 Status Register (SYSCFG_ITLINE9)
257
SYSCFG Interrupt Line 10 Status Register (SYSCFG_ITLINE10)
258
SYSCFG Interrupt Line 11 Status Register (SYSCFG_ITLINE11)
258
SYSCFG Interrupt Line 12 Status Register (SYSCFG_ITLINE12)
259
SYSCFG Interrupt Line 13 Status Register (SYSCFG_ITLINE13)
259
SYSCFG Interrupt Line 14 Status Register (SYSCFG_ITLINE14)
260
SYSCFG Interrupt Line 15 Status Register (SYSCFG_ITLINE15)
260
SYSCFG Interrupt Line 16 Status Register (SYSCFG_ITLINE16)
260
SYSCFG Interrupt Line 17 Status Register (SYSCFG_ITLINE17)
261
SYSCFG Interrupt Line 18 Status Register (SYSCFG_ITLINE18)
261
SYSCFG Interrupt Line 19 Status Register (SYSCFG_ITLINE19)
261
SYSCFG Interrupt Line 20 Status Register (SYSCFG_ITLINE20)
262
SYSCFG Interrupt Line 21 Status Register (SYSCFG_ITLINE21)
262
SYSCFG Interrupt Line 22 Status Register (SYSCFG_ITLINE22)
262
SYSCFG Interrupt Line 23 Status Register (SYSCFG_ITLINE23)
263
SYSCFG Interrupt Line 24 Status Register (SYSCFG_ITLINE24)
263
SYSCFG Interrupt Line 25 Status Register (SYSCFG_ITLINE25)
264
SYSCFG Interrupt Line 26 Status Register (SYSCFG_ITLINE26)
264
SYSCFG Interrupt Line 27 Status Register (SYSCFG_ITLINE27)
264
SYSCFG Interrupt Line 28 Status Register (SYSCFG_ITLINE28)
265
SYSCFG Interrupt Line 29 Status Register (SYSCFG_ITLINE29)
265
SYSCFG Interrupt Line 30 Status Register (SYSCFG_ITLINE30)
265
SYSCFG Interrupt Line 31 Status Register (SYSCFG_ITLINE31)
266
SYSCFG Register Map
266
Table 44. SYSCFG Register Map and Reset Values
266
Interconnect Matrix
270
Introduction
270
Connection Summary
270
Table 45. Interconnect Matrix
270
Interconnection Details
271
From TIM1, TIM2, TIM3, TIM4, TIM15, TIM16, and TIM17, to TIM1, TIM2, TIM3, TIM4, and TIM15
271
From TIM1, TIM2, TIM3, TIM4, TIM6, TIM15, and EXTI, to ADC
272
From ADC to TIM1
272
From TIM1, TIM2, TIM3, TIM4, TIM6, TIM7, TIM15, LPTIM1, LPTIM2
273
And EXTI, to DAC
273
From HSE, LSE, LSI, MCO, MCO2, RTC and TAMP, to TIM2, TIM14
273
TIM16, and TIM17
273
From RTC, TAMP, COMP1, COMP2, and COMP3 to LPTIM1
274
And LPTIM2
274
From TIM1, TIM2, TIM3, TIM4, and TIM15, to COMP1, COMP2
274
And COMP3
274
From Internal Analog Sources to ADC
274
From COMP1, COMP2, and COMP3 to TIM1, TIM2, TIM3, TIM4, TIM15
275
TIM16, and TIM17
275
From System Errors to TIM1, TIM2, TIM3, TIM4, TIM15, TIM16
275
And TIM17
275
From TIM16, TIM17, USART1, and USART4, to IRTIM
276
From TIM14, LPTIM1, and LPTIM2, to DMAMUX
276
Direct Memory Access Controller (DMA)
277
Introduction
277
DMA Main Features
277
DMA Implementation
278
Dma
278
DMA Request Mapping
278
DMA Functional Description
278
DMA Block Diagram
278
Table 46. DMA Implementation
278
DMA Pins and Internal Signals
279
DMA Transfers
279
Table 47. DMA Internal Input/Output Signals
279
Figure 22. DMA Block Diagram
279
DMA Arbitration
280
DMA Channels
281
DMA Data Width, Alignment and Endianness
284
Table 48. Programmable Data Width and Endian Behavior (When PINC = MINC = 1)
285
DMA Error Management
286
DMA Interrupts
286
DMA Registers
286
Table 49. DMA Interrupt Requests
286
DMA Interrupt Status Register (DMA_ISR)
287
DMA Interrupt Flag Clear Register (DMA
289
DMA Channel X Configuration Register (Dma_Ccrx)
290
DMA Channel X Number of Data to Transfer Register (Dma_Cndtrx)
293
DMA Channel X Peripheral Address Register (Dma_Cparx)
294
DMA Channel X Memory Address Register (Dma_Cmarx)
294
DMA Register Map
295
Table 50. DMA Register Map and Reset Values
295
DMA Request Multiplexer (DMAMUX)
298
Introduction
298
DMAMUX Main Features
299
DMAMUX Implementation
299
DMAMUX Instantiation
299
DMAMUX Mapping
299
Table 51. DMAMUX Instantiation
299
Table 52. DMAMUX: Assignment of Multiplexer Inputs to Resources
300
Table 53. DMAMUX: Assignment of Trigger Inputs to Resources
300
Table 54. DMAMUX: Assignment of Synchronization Inputs to Resources
301
DMAMUX Functional Description
302
DMAMUX Block Diagram
302
Figure 23. DMAMUX Block Diagram
302
DMAMUX Signals
303
DMAMUX Channels
303
DMAMUX Request Line Multiplexer
303
Table 55. DMAMUX Signals
303
Figure 24. Synchronization Mode of the DMAMUX Request Line Multiplexer Channel
305
Figure 25. Event Generation of the DMA Request Line Multiplexer Channel
305
DMAMUX Request Generator
306
DMAMUX Interrupts
307
Table 56. DMAMUX Interrupts
307
DMAMUX Registers
308
DMAMUX Request Line Multiplexer Channel X Configuration Register
308
(Dmamux_Cxcr)
308
DMAMUX Request Line Multiplexer Interrupt Channel Status Register
309
(Dmamux_Csr)
309
DMAMUX Request Line Multiplexer Interrupt Clear Flag Register
309
(Dmamux_Cfr)
309
DMAMUX Request Generator Channel X Configuration Register (Dmamux_Rgxcr)
310
DMAMUX Request Generator Interrupt Status Register (DMAMUX_RGSR)
311
DMAMUX Request Generator Interrupt Clear Flag Register (DMAMUX_RGCFR)
311
DMAMUX Register Map
312
Table 57. DMAMUX Register Map and Reset Values
312
Nested Vectored Interrupt Controller (NVIC)
314
Main Features
314
Systick Calibration Value Register
314
Interrupt and Exception Vectors
314
Table 58. Vector Table
314
Extended Interrupt and Event Controller (EXTI)
317
EXTI Main Features
317
EXTI Block Diagram
317
Table 59. EXTI Signal Overview
318
Table 60. EVG Pin Overview
318
Figure 26. EXTI Block Diagram
318
EXTI Connections between Peripherals and CPU
319
EXTI Functional Description
319
EXTI Configurable Event Input Wakeup
320
Table 61. EXTI Event Input Configurations and Register Control
320
Figure 27. Configurable Event Trigger Logic CPU Wakeup
320
EXTI Direct Event Input Wakeup
321
EXTI Mux
321
Figure 28. Direct Event Trigger Logic CPU Wakeup
321
Table 62. EXTI Line Connections
322
Figure 29. EXTI GPIO Mux
322
EXTI Functional Behavior
323
Table 63. Masking Functionality
323
EXTI Registers
324
EXTI Rising Trigger Selection Register (EXTI_RTSR1)
324
Table 64. EXTI Register Map Sections
324
EXTI Falling Trigger Selection Register 1 (EXTI_FTSR1)
325
EXTI Software Interrupt Event Register 1 (EXTI_SWIER1)
325
EXTI Rising Edge Pending Register 1 (EXTI_RPR1)
326
EXTI Falling Edge Pending Register 1 (EXTI_FPR1)
327
EXTI Rising Trigger Selection Register 2 (EXTI_RTSR2)
328
EXTI Falling Trigger Selection Register 2 (EXTI_FTSR2)
328
EXTI Software Interrupt Event Register 2 (EXTI_SWIER2)
329
EXTI Rising Edge Pending Register 2 (EXTI_RPR2)
329
EXTI Falling Edge Pending Register 2 (EXTI_FPR2)
330
EXTI External Interrupt Selection Register (Exti_Exticrx)
330
EXTI CPU Wakeup with Interrupt Mask Register (EXTI_IMR1)
332
EXTI CPU Wakeup with Event Mask Register (EXTI_EMR1)
332
EXTI CPU Wakeup with Interrupt Mask Register (EXTI_IMR2)
333
EXTI CPU Wakeup with Event Mask Register (EXTI_EMR2)
333
EXTI Register Map
334
Table 65. EXTI Controller Register Map and Reset Values
334
Cyclic Redundancy Check Calculation Unit (CRC)
336
Introduction
336
CRC Main Features
336
CRC Functional Description
337
CRC Block Diagram
337
CRC Internal Signals
337
CRC Operation
337
Table 66. CRC Internal Input/Output Signals
337
Figure 30. CRC Calculation Unit Block Diagram
337
CRC Registers
339
CRC Data Register (CRC_DR)
339
CRC Independent Data Register (CRC_IDR)
339
CRC Control Register (CRC_CR)
340
CRC Initial Value (CRC_INIT)
341
CRC Polynomial (CRC_POL)
341
CRC Register Map
342
Table 67. CRC Register Map and Reset Values
342
Analog-To-Digital Converter (ADC)
343
Introduction
343
ADC Main Features
344
ADC Functional Description
345
ADC Pins and Internal Signals
345
Table 68. ADC Input/Output Pins
345
Figure 31. ADC Block Diagram
345
ADC Voltage Regulator (ADVREGEN)
346
Table 69. ADC Internal Input/Output Signals
346
Table 70. External Triggers
346
Calibration (ADCAL)
347
ADC On-Off Control (ADEN, ADDIS, ADRDY)
348
Figure 32. ADC Calibration
348
Figure 33. Calibration Factor Forcing
348
Figure 34. Enabling/Disabling the ADC
349
ADC Clock (CKMODE, PRESC[3:0])
350
Figure 35. ADC Clock Scheme
350
Table 71. Latency between Trigger and Start of Conversion
351
ADC Connectivity
352
Figure 36. ADC Connectivity
352
Configuring the ADC
353
Channel Selection (CHSEL, SCANDIR, CHSELRMOD)
353
Programmable Sampling Time (Smpx[2:0])
354
Single Conversion Mode (CONT = 0)
355
Continuous Conversion Mode (CONT = 1)
355
Starting Conversions (ADSTART)
356
Timings
357
Figure 37. Analog to Digital Conversion Time
357
Figure 38. ADC Conversion Timings
357
Stopping an Ongoing Conversion (ADSTP)
358
Conversion on External Trigger and Trigger Polarity (EXTSEL, EXTEN)
358
Table 72. Configuring the Trigger Polarity
358
Figure 39. Stopping an Ongoing Conversion
358
Discontinuous Mode (DISCEN)
359
Programmable Resolution (RES) - Fast Conversion Mode
359
End of Conversion, End of Sampling Phase (EOC, EOSMP Flags)
360
End of Conversion Sequence (EOS Flag)
360
Table 73. Tsar Timings Depending on Resolution
360
Example Timing Diagrams
361
Hardware/Software Triggers)
361
Figure 40. Single Conversions of a Sequence, Software Trigger
361
Figure 41. Continuous Conversion of a Sequence, Software Trigger
361
Figure 42. Single Conversions of a Sequence, Hardware Trigger
362
Figure 43. Continuous Conversions of a Sequence, Hardware Trigger
362
Low Frequency Trigger Mode
363
Data Management
363
Data Register and Data Alignment (ADC_DR, ALIGN)
363
ADC Overrun (OVR, OVRMOD)
363
Figure 44. Data Alignment and Resolution (Oversampling Disabled: OVSE = 0)
363
Figure 45. Example of Overrun (OVR)
364
Managing a Sequence of Data Converted Without Using the DMA
365
Managing Converted Data Without Using the DMA Without Overrun
365
Managing Converted Data Using the DMA
365
Low-Power Features
366
Wait Mode Conversion
366
Auto-Off Mode (AUTOFF)
367
Figure 46. Wait Mode Conversion (Continuous Mode, Software Trigger)
367
Figure 48. Behavior with WAIT = 1, AUTOFF = 1
367
Figure 47. Behavior with WAIT = 0, AUTOFF = 1
368
Analog Window Watchdog (AWD1EN, AWD1SGL, AWD1CH, Adc_Awdxcr, Adc_Awdxtr)
369
Description of Analog Watchdog 1
369
Table 74. Analog Watchdog Comparison
369
Figure 49. Analog Watchdog Guarded Area
369
Description of Analog Watchdog 2 and 3
370
Adc_Awdx_Out Output Signal Generation
370
Table 75. Analog Watchdog 1 Channel Selection
370
Figure 50. Adc_Awdx_Out Signal Generation
371
Figure 51. Adc_Awdx_Out Signal Generation (Awdx Flag Not Cleared by Software)
371
Analog Watchdog Threshold Control
372
Figure 52. Adc_Awdx_Out Signal Generation (on a Single Channel)
372
Figure 53. Analog Watchdog Threshold Update
372
Oversampler
373
Figure 54. 20-Bit to 16-Bit Result Truncation
373
Table 76. Maximum Output Results Vs N and M. Grayed Values Indicates Truncation
374
Figure 55. Numerical Example with 5-Bits Shift and Rounding
374
ADC Operating Modes Supported When Oversampling
375
Analog Watchdog
375
Triggered Mode
375
Temperature Sensor and Internal Reference Voltage
376
Figure 56. Triggered Oversampling Mode (TOVS Bit = 1)
376
Figure 57. Temperature Sensor and VREFINT Channel Block Diagram
377
Battery Voltage Monitoring
378
ADC Interrupts
379
Table 77. ADC Interrupts
379
Figure 58. VBAT Channel Block Diagram
379
ADC Registers
381
ADC Interrupt and Status Register (ADC_ISR)
381
ADC Interrupt Enable Register (ADC_IER)
383
ADC Control Register (ADC_CR)
385
ADC Configuration Register 1 (ADC_CFGR1)
387
ADC Configuration Register 2 (ADC_CFGR2)
391
ADC Sampling Time Register (ADC_SMPR)
392
ADC Watchdog Threshold Register (ADC_AWD1TR)
393
ADC Watchdog Threshold Register (ADC_AWD2TR)
394
ADC Channel Selection Register [Alternate] (ADC_CHSELR)
395
ADC Channel Selection Register [Alternate] (ADC_CHSELR)
396
ADC Watchdog Threshold Register (ADC_AWD3TR)
398
ADC Data Register (ADC_DR)
398
ADC Analog Watchdog 2 Configuration Register (ADC_AWD2CR)
399
ADC Analog Watchdog 3 Configuration Register (ADC_AWD3CR)
399
ADC Calibration Factor (ADC_CALFACT)
400
ADC Common Configuration Register (ADC_CCR)
400
ADC Register Map
402
Table 78. ADC Register Map and Reset Values
402
Digital-To-Analog Converter (DAC)
404
Introduction
404
DAC Main Features
404
Figure 59. Dual-Channel DAC Block Diagram
404
DAC Implementation
405
Table 79. DAC Features
405
DAC Functional Description
406
DAC Block Diagram
406
DAC Pins and Internal Signals
407
Table 80. DAC Input/Output Pins
407
Table 81. DAC Internal Input/Output Signals
407
DAC Channel Enable
408
DAC Data Format
408
Table 82. DAC Interconnection
408
Figure 60. Data Registers in Single DAC Channel Mode
409
Figure 61. Data Registers in Dual DAC Channel Mode
409
DAC Conversion
410
DAC Output Voltage
410
DAC Trigger Selection
410
Figure 62. Timing Diagram for Conversion with Trigger Disabled TEN = 0
410
DMA Requests
411
Noise Generation
411
Figure 63. DAC LFSR Register Calculation Algorithm
412
Figure 64. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
412
Triangle-Wave Generation
413
Figure 65. DAC Triangle Wave Generation
413
Figure 66. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
413
DAC Channel Modes
414
Table 83. Sample and Refresh Timings
415
Table 84. Channel Output Modes Summary
416
Figure 67. DAC Sample and Hold Mode Phase Diagram
416
DAC Channel Buffer Calibration
417
Dual DAC Channel Conversion Modes
418
Available)
418
DAC Low-Power Modes
422
Table 85. Effect of Low-Power Modes on DAC
422
DAC Interrupts
423
Table 86. DAC Interrupts
423
DAC Registers
424
DAC Control Register (DAC_CR)
424
DAC Software Trigger Register (DAC_SWTRGR)
427
DAC Channel1 12-Bit Right-Aligned Data Holding Register (DAC_DHR12R1)
428
DAC Channel1 12-Bit Left Aligned Data Holding Register
428
(Dac_Dhr12L1)
428
DAC Channel1 8-Bit Right Aligned Data Holding Register (DAC_DHR8R1)
429
DAC Channel2 12-Bit Right Aligned Data Holding Register (DAC_DHR12R2)
429
DAC Channel2 12-Bit Left Aligned Data Holding Register
430
(Dac_Dhr12L2)
430
DAC Channel2 8-Bit Right-Aligned Data Holding Register (DAC_DHR8R2)
430
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)
431
Dual DAC 12-Bit Left Aligned Data Holding Register
431
(Dac_Dhr12Ld)
431
Dual DAC 8-Bit Right Aligned Data Holding Register
432
(Dac_Dhr8Rd)
432
DAC Channel1 Data Output Register (DAC_DOR1)
432
DAC Channel2 Data Output Register (DAC_DOR2)
433
DAC Status Register (DAC_SR)
433
DAC Calibration Control Register (DAC_CCR)
435
DAC Mode Control Register (DAC_MCR)
435
DAC Channel1 Sample and Hold Sample Time Register
437
(Dac_Shsr1)
437
DAC Channel2 Sample and Hold Sample Time Register
437
(Dac_Shsr2)
437
DAC Sample and Hold Time Register (DAC_SHHR)
438
DAC Sample and Hold Refresh Time Register (DAC_SHRR)
438
DAC Register Map
440
Table 87. DAC Register Map and Reset Values
440
Voltage Reference Buffer (VREFBUF)
442
Introduction
442
VREFBUF Functional Description
442
Table 88. VREF Buffer Modes
442
VREFBUF Registers
443
VREFBUF Control and Status Register (VREFBUF_CSR)
443
VREFBUF Calibration Control Register (VREFBUF_CCR)
444
VREFBUF Register Map
444
Table 89. VREFBUF Register Map and Reset Values
444
Comparator (COMP)
445
Introduction
445
COMP Main Features
445
COMP Functional Description
446
COMP Block Diagram
446
COMP Pins and Internal Signals
446
Table 90. COMP1 Non-Inverting Input Assignment
446
Figure 68. Comparator Block Diagram
446
Table 91. COMP1 Inverting Input Assignment
447
Table 92. COMP2 Non-Inverting Input Assignment
447
Table 93. COMP2 Inverting Input Assignment
447
COMP Reset and Clocks
448
Comparator LOCK Mechanism
448
Table 94. COMP3 Non-Inverting Input Assignment
448
Table 95. COMP3 Inverting Input Assignment
448
Window Comparator
449
Hysteresis
449
Figure 69. Window Mode
449
Figure 70. Comparator Hysteresis
449
Comparator Output Blanking Function
450
COMP Power and Speed Modes
450
Figure 71. Comparator Output Blanking
450
COMP Low-Power Modes
451
COMP Interrupts
451
COMP Registers
451
Comparator 1 Control and Status Register (COMP1_CSR)
451
Table 96. Comparator Behavior in the Low Power Modes
451
Table 97. Interrupt Control Bits
451
Comparator 2 Control and Status Register (COMP2_CSR)
453
Comparator 3 Control and Status Register (COMP3_CSR)
455
COMP Register Map
458
Table 98. COMP Register Map and Reset Values
458
True Random Number Generator (RNG)
459
Introduction
459
RNG Main Features
459
RNG Functional Description
460
RNG Block Diagram
460
RNG Internal Signals
460
Table 99. RNG Internal Input/Output Signals
460
Figure 72. RNG Block Diagram
460
Random Number Generation
461
Figure 73. Entropy Source Model
461
RNG Initialization
463
RNG Operation
464
Figure 74. RNG Initialization Overview
464
RNG Clocking
465
Error Management
465
RNG Low-Power Usage
466
RNG Interrupts
467
RNG Processing Time
467
RNG Entropy Source Validation
467
Introduction
467
Validation Conditions
467
Table 100. RNG Interrupt Requests
467
Data Collection
468
RNG Registers
469
RNG Control Register (RNG_CR)
469
RNG Status Register (RNG_SR)
470
RNG Data Register (RNG_DR)
471
RNG Register Map
472
Table 101. RNG Register Map and Reset Map
472
AES Hardware Accelerator (AES)
473
Introduction
473
AES Main Features
473
AES Implementation
474
AES Functional Description
474
AES Block Diagram
474
AES Internal Signals
474
Table 102. AES Internal Input/Output Signals
474
Figure 75. AES Block Diagram
474
AES Cryptographic Core
475
Figure 76. ECB Encryption and Decryption Principle
476
Figure 77. CBC Encryption and Decryption Principle
477
Figure 78. CTR Encryption and Decryption Principle
478
Figure 79. GCM Encryption and Authentication Principle
479
Figure 80. GMAC Authentication Principle
479
AES Procedure to Perform a Cipher Operation
480
Figure 81. CCM Encryption and Authentication Principle
480
AES Decryption Round Key Preparation
483
AES Ciphertext Stealing and Data Padding
483
AES Task Suspend and Resume
484
AES Basic Chaining Modes (ECB, CBC)
484
Figure 82. Example of Suspend Mode Management
484
Figure 83. ECB Encryption
485
Figure 84. ECB Decryption
485
Figure 85. CBC Encryption
486
Figure 86. CBC Decryption
486
Figure 87. ECB/CBC Encryption (Mode 1)
487
Figure 88. ECB/CBC Decryption (Mode 3)
488
AES Counter (CTR) Mode
489
Figure 89. Message Construction in CTR Mode
490
Figure 90. CTR Encryption
490
Table 103. CTR Mode Initialization Vector Definition
491
Figure 91. CTR Decryption
491
AES Galois/Counter Mode (GCM)
492
Figure 92. Message Construction in GCM
492
Table 104. GCM Last Block Definition
493
Table 105. GCM Mode IVI Bitfield Initialization
494
Figure 93. GCM Authenticated Encryption
494
AES Galois Message Authentication Code (GMAC)
497
Figure 94. Message Construction in GMAC Mode
498
Figure 95. GMAC Authentication Mode
498
AES Counter with CBC-MAC (CCM)
499
Figure 96. Message Construction in CCM Mode
499
Table 106. Initialization of Aes_Ivrx Registers in CCM Mode
501
Figure 97. CCM Mode Authenticated Encryption
501
AES Data Registers and Data Swapping
505
Figure 98. 128-Bit Block Construction with Respect to Data Swap
506
AES Key Registers
507
AES Initialization Vector Registers
507
AES DMA Interface
507
Table 107. Key Endianness in Aes_Keyrx Registers (128- or 256-Bit Key Length)
507
Figure 99. DMA Transfer of a 128-Bit Data Block During Input Phase
508
Figure 100. DMA Transfer of a 128-Bit Data Block During Output Phase
508
AES Error Management
509
AES Interrupts
509
AES Processing Latency
510
Table 108. AES Interrupt Requests
510
Table 109. Processing Latency for ECB, CBC and CTR
510
Table 110. Processing Latency for GCM and CCM (in Clock Cycles)
510
AES Registers
511
AES Control Register (AES_CR)
511
AES Status Register (AES_SR)
513
AES Data Input Register (AES_DINR)
514
AES Data Output Register (AES_DOUTR)
515
AES Key Register 0 (AES_KEYR0)
516
AES Key Register 1 (AES_KEYR1)
516
AES Key Register 2 (AES_KEYR2)
517
AES Key Register 3 (AES_KEYR3)
517
AES Initialization Vector Register 0 (AES_IVR0)
517
AES Initialization Vector Register 1 (AES_IVR1)
518
AES Initialization Vector Register 2 (AES_IVR2)
518
AES Initialization Vector Register 3 (AES_IVR3)
518
AES Key Register 4 (AES_KEYR4)
519
AES Key Register 5 (AES_KEYR5)
519
AES Key Register 6 (AES_KEYR6)
519
AES Key Register 7 (AES_KEYR7)
520
AES Suspend Registers (Aes_Suspxr)
520
AES Register Map
521
Table 111. AES Register Map and Reset Values
521
Advanced-Control Timer (TIM1)
523
TIM1 Introduction
523
TIM1 Main Features
524
Figure 101. Advanced-Control Timer Block Diagram
525
TIM1 Functional Description
526
Time-Base Unit
526
Figure 102. Counter Timing Diagram with Prescaler Division Change from 1 to 2
527
Figure 103. Counter Timing Diagram with Prescaler Division Change from 1 to 4
527
Counter Modes
528
Figure 104. Counter Timing Diagram, Internal Clock Divided by 1
529
Figure 105. Counter Timing Diagram, Internal Clock Divided by 2
529
Figure 106. Counter Timing Diagram, Internal Clock Divided by 4
530
Figure 107. Counter Timing Diagram, Internal Clock Divided by N
530
Figure 108. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
531
Figure 109. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
531
Figure 110. Counter Timing Diagram, Internal Clock Divided by 1
533
Figure 111. Counter Timing Diagram, Internal Clock Divided by 2
533
Figure 112. Counter Timing Diagram, Internal Clock Divided by 4
534
Figure 113. Counter Timing Diagram, Internal Clock Divided by N
534
Figure 114. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
535
Figure 115. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
536
Figure 116. Counter Timing Diagram, Internal Clock Divided by 2
537
Figure 117. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
537
Figure 118. Counter Timing Diagram, Internal Clock Divided by N
538
Figure 119. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
538
Repetition Counter
539
Figure 120. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
539
Figure 121. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
540
External Trigger Input
541
Figure 122. External Trigger Input Block
541
Figure 123. TIM1 ETR Input Circuitry
541
Clock Selection
542
Figure 124. Control Circuit in Normal Mode, Internal Clock Divided by 1
542
Figure 125. TI2 External Clock Connection Example
543
Figure 126. Control Circuit in External Clock Mode 1
544
Figure 127. External Trigger Input Block
544
Figure 128. Control Circuit in External Clock Mode 2
545
Capture/Compare Channels
546
Figure 129. Capture/Compare Channel (Example: Channel 1 Input Stage)
546
Figure 130. Capture/Compare Channel 1 Main Circuit
546
Figure 131. Output Stage of Capture/Compare Channel (Channel 1, Idem Ch. 2 and 3)
547
Figure 132. Output Stage of Capture/Compare Channel (Channel 4)
547
Input Capture Mode
548
Figure 133. Output Stage of Capture/Compare Channel (Channel 5, Idem Ch. 6)
548
PWM Input Mode
549
Forced Output Mode
550
Figure 134. PWM Input Mode Timing
550
Output Compare Mode
551
PWM Mode
552
Figure 135. Output Compare Mode, Toggle on OC1
552
Figure 136. Edge-Aligned PWM Waveforms (ARR=8)
553
Figure 137. Center-Aligned PWM Waveforms (ARR=8)
554
Asymmetric PWM Mode
555
Combined PWM Mode
556
Figure 138. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle
556
Combined 3-Phase PWM Mode
557
Figure 139. Combined PWM Mode on Channel 1 and 3
557
Complementary Outputs and Dead-Time Insertion
558
Figure 140. 3-Phase Combined PWM Signals with Multiple Trigger Pulses Per Period
558
Figure 141. Complementary Output with Dead-Time Insertion
559
Figure 142. Dead-Time Waveforms with Delay Greater than the Negative Pulse
559
Using the Break Function
560
Figure 143. Dead-Time Waveforms with Delay Greater than the Positive Pulse
560
Figure 144. Break and Break2 Circuitry Overview
562
Figure 145. Various Output Behavior in Response to a Break Event on BRK (OSSI = 1)
564
Table 112. Behavior of Timer Outputs Versus BRK/BRK2 Inputs
565
Figure 146. PWM Output State Following BRK and BRK2 Pins Assertion (OSSI=1)
565
Bidirectional Break Inputs
566
Figure 147. PWM Output State Following BRK Assertion (OSSI=0)
566
Table 113. Break Protection Disarming Conditions
567
Figure 148. Output Redirection (BRK2 Request Not Represented)
567
Clearing the Ocxref Signal on an External Event
568
Figure 149. Clearing Timx Ocxref
568
6-Step PWM Generation
569
Figure 150. 6-Step Generation, COM Example (OSSR=1)
569
One-Pulse Mode
570
Figure 151. Example of One Pulse Mode
570
Retriggerable One Pulse Mode
571
Encoder Interface Mode
572
Figure 152. Retriggerable One Pulse Mode
572
Table 114. Counting Direction Versus Encoder Signals
573
Figure 153. Example of Counter Operation in Encoder Interface Mode
573
UIF Bit Remapping
574
Figure 154. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
574
Timer Input XOR Function
575
Interfacing with Hall Sensors
575
Figure 155. Measuring Time Interval between Edges on 3 Signals
575
Figure 156. Example of Hall Sensor Interface
577
Timer Synchronization
578
Figure 157. Control Circuit in Reset Mode
578
Figure 158. Control Circuit in Gated Mode
579
Figure 159. Control Circuit in Trigger Mode
580
Figure 160. Control Circuit in External Clock Mode 2 + Trigger Mode
581
ADC Synchronization
582
DMA Burst Mode
582
Debug Mode
583
TIM1 Registers
584
TIM1 Control Register 1 (TIM1_CR1)
584
TIM1 Control Register 2 (TIM1_CR2)
585
TIM1 Slave Mode Control Register (TIM1_SMCR)
588
TIM1 Dma/Interrupt Enable Register (TIM1_DIER)
590
Table 115. TIM1 Internal Trigger Connection
590
TIM1 Status Register (TIM1_SR)
592
TIM1 Event Generation Register (TIM1_EGR)
594
TIM1 Capture/Compare Mode Register 1 [Alternate]
595
(Tim1_Ccmr1)
595
TIM1 Capture/Compare Mode Register 1 [Alternate]
596
(Tim1_Ccmr1)
596
TIM1 Capture/Compare Mode Register 2 [Alternate]
599
(Tim1_Ccmr2)
599
TIM1 Capture/Compare Mode Register 2 [Alternate]
600
(Tim1_Ccmr2)
600
TIM1 Capture/Compare Enable Register
602
(Tim1_Ccer)
602
Table 116. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
604
TIM1 Counter (TIM1_CNT)
605
TIM1 Prescaler (TIM1_PSC)
605
TIM1 Auto-Reload Register (TIM1_ARR)
605
TIM1 Repetition Counter Register (TIM1_RCR)
606
TIM1 Capture/Compare Register 1 (TIM1_CCR1)
606
TIM1 Capture/Compare Register 2 (TIM1_CCR2)
607
TIM1 Capture/Compare Register 3 (TIM1_CCR3)
607
TIM1 Capture/Compare Register 4 (TIM1_CCR4)
608
TIM1 Break and Dead-Time Register
608
(Tim1_Bdtr)
608
TIM1 DMA Control Register (TIM1_DCR)
612
TIM1 DMA Address for Full Transfer
613
(Tim1_Dmar)
613
TIM1 Option Register 1 (TIM1_OR1)
614
TIM1 Capture/Compare Mode Register 3
614
(Tim1_Ccmr3)
614
TIM1 Capture/Compare Register 5 (TIM1_CCR5)
615
TIM1 Capture/Compare Register 6 (TIM1_CCR6)
616
TIM1 Alternate Function Option Register 1 (TIM1_AF1)
617
TIM1 Alternate Function Register 2 (TIM1_AF2)
619
TIM1 Timer Input Selection Register (TIM1_TISEL)
620
TIM1 Register Map
622
Table 117. TIM1 Register Map and Reset Values
622
General-Purpose Timers (TIM2/TIM3/TIM4)
625
TIM2/TIM3/TIM4 Introduction
625
TIM2/TIM3/TIM4 Main Features
625
Figure 161. General-Purpose Timer Block Diagram
626
TIM2/TIM3/TIM4 Functional Description
627
Time-Base Unit
627
Figure 162. Counter Timing Diagram with Prescaler Division Change from 1 to 2
628
Figure 163. Counter Timing Diagram with Prescaler Division Change from 1 to 4
628
Counter Modes
629
Figure 164. Counter Timing Diagram, Internal Clock Divided by 1
629
Figure 165. Counter Timing Diagram, Internal Clock Divided by 2
630
Figure 166. Counter Timing Diagram, Internal Clock Divided by 4
630
Figure 167. Counter Timing Diagram, Internal Clock Divided by N
631
Figure 168. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
631
Figure 169. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
632
Figure 170. Counter Timing Diagram, Internal Clock Divided by 1
633
Figure 171. Counter Timing Diagram, Internal Clock Divided by 2
633
Figure 172. Counter Timing Diagram, Internal Clock Divided by 4
634
Figure 173. Counter Timing Diagram, Internal Clock Divided by N
634
Figure 174. Counter Timing Diagram, Update Event When Repetition Counter
635
Figure 175. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
636
Figure 176. Counter Timing Diagram, Internal Clock Divided by 2
637
Figure 177. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
637
Figure 178. Counter Timing Diagram, Internal Clock Divided by N
638
Figure 179. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
638
Clock Selection
639
Figure 180. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
639
Figure 181. Control Circuit in Normal Mode, Internal Clock Divided by 1
640
Figure 182. TI2 External Clock Connection Example
640
Figure 183. Control Circuit in External Clock Mode 1
641
Figure 184. External Trigger Input Block
642
Capture/Compare Channels
643
Figure 185. Control Circuit in External Clock Mode 2
643
Figure 186. Capture/Compare Channel (Example: Channel 1 Input Stage)
643
Figure 187. Capture/Compare Channel 1 Main Circuit
644
Figure 188. Output Stage of Capture/Compare Channel (Channel 1)
644
Input Capture Mode
645
PWM Input Mode
646
Figure 189. PWM Input Mode Timing
646
Forced Output Mode
647
Output Compare Mode
647
PWM Mode
648
Figure 190. Output Compare Mode, Toggle on OC1
648
Figure 191. Edge-Aligned PWM Waveforms (ARR=8)
649
Figure 192. Center-Aligned PWM Waveforms (ARR=8)
651
Asymmetric PWM Mode
652
Combined PWM Mode
652
Figure 193. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle
652
Clearing the Ocxref Signal on an External Event
653
Figure 194. Combined PWM Mode on Channels 1 and 3
653
Figure 195. Clearing Timx Ocxref
654
One-Pulse Mode
655
Figure 196. Example of One-Pulse Mode
655
22.3.14 Retriggerable One Pulse Mode
656
Encoder Interface Mode
657
Figure 197. Retriggerable One-Pulse Mode
657
Table 118. Counting Direction Versus Encoder Signals
658
Figure 198. Example of Counter Operation in Encoder Interface Mode
658
UIF Bit Remapping
659
Timer Input XOR Function
659
Figure 199. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
659
Timers and External Trigger Synchronization
660
Figure 200. Control Circuit in Reset Mode
660
Figure 201. Control Circuit in Gated Mode
661
Figure 202. Control Circuit in Trigger Mode
662
Timer Synchronization
663
Figure 203. Control Circuit in External Clock Mode 2 + Trigger Mode
663
Figure 204. Master/Slave Timer Example
663
Figure 205. Master/Slave Connection Example with 1 Channel Only Timers
664
Figure 206. Gating TIM2 with OC1REF of TIM3
665
Figure 207. Gating TIM2 with Enable of TIM3
666
Figure 208. Triggering TIM2 with Update of TIM3
666
Figure 209. Triggering TIM2 with Enable of TIM3
667
DMA Burst Mode
668
Figure 210. Triggering TIM3 and TIM2 with TIM3 TI1 Input
668
Debug Mode
669
TIM2/TIM3/TIM4 Registers
670
Timx Control Register 1 (Timx_Cr1)(X = 2 to 4)
670
Timx Control Register 2 (Timx_Cr2)(X = 2 to 4)
671
Timx Slave Mode Control Register (Timx_Smcr)(X = 2 to 4)
673
Timx Dma/Interrupt Enable Register (Timx_Dier)(X = 2 to 4)
676
Table 119. Timx Internal Trigger Connection
676
Timx Status Register (Timx_Sr)(X = 2 to 4)
677
Timx Event Generation Register (Timx_Egr)(X = 2 to 4)
679
Timx Capture/Compare Mode Register 1 [Alternate] (Timx_Ccmr1)
680
Timx Capture/Compare Mode Register 1 [Alternate] (Timx_Ccmr1)
682
Timx Capture/Compare Mode Register 2 [Alternate] (Timx_Ccmr2)
684
Timx Capture/Compare Mode Register 2 [Alternate] (Timx_Ccmr2)
685
(Timx_Ccer)(X = 2 to 4)
686
Timx Counter [Alternate] (Timx_Cnt)(X = 2 to 4)
687
Table 120. Output Control Bit for Standard Ocx Channels
687
Timx Counter [Alternate] (Timx_Cnt)(X = 2 to 4)
688
Timx Prescaler (Timx_Psc)(X = 2 to 4)
688
Timx Auto-Reload Register (Timx_Arr)(X = 2 to 4)
689
Timx Capture/Compare Register 1 (Timx_Ccr1)(X = 2 to 4)
689
Timx Capture/Compare Register 2 (Timx_Ccr2)(X = 2 to 4)
690
Timx Capture/Compare Register 3 (Timx_Ccr3)(X = 2 to 4)
690
Timx Capture/Compare Register 4 (Timx_Ccr4)(X = 2 to 4)
691
Timx DMA Control Register (Timx_Dcr)(X = 2 to 4)
692
Timx DMA Address for Full Transfer (Timx_Dmar)(X = 2 to 4)
692
TIM2 Option Register 1 (TIM2_OR1)
692
TIM3 Option Register 1 (TIM3_OR1)
693
TIM4 Option Register 1 (TIM4_OR1)
694
TIM2 Alternate Function Option Register 1 (TIM2_AF1)
694
TIM3 Alternate Function Option Register 1 (TIM3_AF1)
695
TIM4 Alternate Function Option Register 1 (TIM4_AF1)
695
TIM2 Timer Input Selection Register (TIM2_TISEL)
696
TIM3 Timer Input Selection Register (TIM3_TISEL)
696
TIM4 Timer Input Selection Register (TIM4_TISEL)
697
Timx Register Map
699
Table 121. TIM2/TIM3/TIM4 Register Map and Reset Values
699
Basic Timers (TIM6/TIM7)
702
TIM6/TIM7 Introduction
702
TIM6/TIM7 Main Features
702
Figure 211. Basic Timer Block Diagram
702
TIM6/TIM7 Functional Description
703
Time-Base Unit
703
Figure 212. Counter Timing Diagram with Prescaler Division Change from 1 to 2
704
Figure 213. Counter Timing Diagram with Prescaler Division Change from 1 to 4
704
Counting Mode
705
Figure 214. Counter Timing Diagram, Internal Clock Divided by 1
705
Figure 215. Counter Timing Diagram, Internal Clock Divided by 2
706
Figure 216. Counter Timing Diagram, Internal Clock Divided by 4
706
Figure 217. Counter Timing Diagram, Internal Clock Divided by N
707
UIF Bit Remapping
708
Clock Source
708
Debug Mode
709
TIM6/TIM7 Registers
709
Timx Control Register 1 (Timx_Cr1)(X = 6 to 7)
709
Figure 220. Control Circuit in Normal Mode, Internal Clock Divided by 1
709
Timx Control Register 2 (Timx_Cr2)(X = 6 to 7)
711
Timx Dma/Interrupt Enable Register (Timx_Dier)(X = 6 to 7)
711
Timx Status Register (Timx_Sr)(X = 6 to 7)
712
Timx Event Generation Register (Timx_Egr)(X = 6 to 7)
712
Timx Counter (Timx_Cnt)(X = 6 to 7)
712
Timx Prescaler (Timx_Psc)(X = 6 to 7)
713
Timx Auto-Reload Register (Timx_Arr)(X = 6 to 7)
713
Timx Register Map
714
Table 122. Timx Register Map and Reset Values
714
General-Purpose Timers (TIM14)
715
TIM14 Introduction
715
TIM14 Main Features
715
Figure 221. General-Purpose Timer Block Diagram (TIM14)
716
TIM14 Functional Description
717
Time-Base Unit
717
Figure 222. Counter Timing Diagram with Prescaler Division Change from 1 to 2
718
Figure 223. Counter Timing Diagram with Prescaler Division Change from 1 to 4
718
Counter Modes
719
Figure 224. Counter Timing Diagram, Internal Clock Divided by 1
719
Figure 225. Counter Timing Diagram, Internal Clock Divided by 2
720
Figure 226. Counter Timing Diagram, Internal Clock Divided by 4
720
Figure 227. Counter Timing Diagram, Internal Clock Divided by N
721
Clock Selection
722
Capture/Compare Channels
723
Figure 230. Control Circuit in Normal Mode, Internal Clock Divided by 1
723
Figure 231. Capture/Compare Channel (Example: Channel 1 Input Stage)
723
Input Capture Mode
724
Figure 232. Capture/Compare Channel 1 Main Circuit
724
Figure 233. Output Stage of Capture/Compare Channel (Channel 1)
724
Forced Output Mode
725
Output Compare Mode
726
PWM Mode
727
Figure 234. Output Compare Mode, Toggle on OC1
727
One-Pulse Mode
728
UIF Bit Remapping
728
Figure 235. Edge-Aligned PWM Waveforms (ARR=8)
728
Using Timer Output as Trigger for Other Timers (TIM14)
729
Debug Mode
729
TIM14 Registers
730
TIM14 Control Register 1 (TIM14_CR1)
730
TIM14 Interrupt Enable Register (TIM14_DIER)
731
TIM14 Status Register (TIM14_SR)
731
TIM14 Event Generation Register (TIM14_EGR)
732
TIM14 Capture/Compare Mode Register 1 [Alternate] (TIM14_CCMR1)
733
TIM14 Capture/Compare Enable Register (TIM14_CCER)
736
TIM14 Counter (TIM14_CNT)
737
Table 123. Output Control Bit for Standard Ocx Channels
737
TIM14 Prescaler (TIM14_PSC)
738
TIM14 Auto-Reload Register (TIM14_ARR)
738
TIM14 Capture/Compare Register 1 (TIM14_CCR1)
738
TIM14 Timer Input Selection Register (TIM14_TISEL)
739
TIM14 Register Map
739
Table 124. TIM14 Register Map and Reset Values
739
General-Purpose Timers (TIM15/TIM16/TIM17)
741
TIM15/TIM16/TIM17 Introduction
741
TIM15 Main Features
741
TIM16/TIM17 Main Features
742
Figure 236. TIM15 Block Diagram
743
Figure 237. TIM16/TIM17 Block Diagram
744
TIM15/TIM16/TIM17 Functional Description
745
Time-Base Unit
745
Figure 238. Counter Timing Diagram with Prescaler Division Change from 1 to 2
746
Figure 239. Counter Timing Diagram with Prescaler Division Change from 1 to 4
746
Counter Modes
747
Figure 240. Counter Timing Diagram, Internal Clock Divided by 1
748
Figure 241. Counter Timing Diagram, Internal Clock Divided by 2
748
Figure 242. Counter Timing Diagram, Internal Clock Divided by 4
749
Figure 243. Counter Timing Diagram, Internal Clock Divided by N
749
Repetition Counter
751
Clock Selection
752
Figure 246. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
752
Figure 247. Control Circuit in Normal Mode, Internal Clock Divided by 1
753
Figure 248. TI2 External Clock Connection Example
753
Capture/Compare Channels
754
Figure 249. Control Circuit in External Clock Mode 1
754
Figure 250. Capture/Compare Channel (Example: Channel 1 Input Stage)
755
Figure 251. Capture/Compare Channel 1 Main Circuit
755
Input Capture Mode
756
Figure 252. Output Stage of Capture/Compare Channel (Channel 1)
756
Figure 253. Output Stage of Capture/Compare Channel (Channel 2 for TIM15)
756
PWM Input Mode (Only for TIM15)
757
Forced Output Mode
758
Figure 254. PWM Input Mode Timing
758
Output Compare Mode
759
PWM Mode
760
Figure 255. Output Compare Mode, Toggle on OC1
760
Combined PWM Mode (TIM15 Only)
761
Figure 256. Edge-Aligned PWM Waveforms (ARR=8)
761
Complementary Outputs and Dead-Time Insertion
762
Figure 257. Combined PWM Mode on Channel 1 and 2
762
Figure 258. Complementary Output with Dead-Time Insertion
763
Figure 259. Dead-Time Waveforms with Delay Greater than the Negative Pulse
763
Using the Break Function
764
Figure 260. Dead-Time Waveforms with Delay Greater than the Positive Pulse
764
Figure 261. Break Circuitry Overview
766
Figure 262. Output Behavior in Response to a Break
768
Bidirectional Break Inputs
769
Table 125. Break Protection Disarming Conditions
769
Figure 263. Output Redirection
770
One-Pulse Mode
771
Figure 264. Example of One Pulse Mode
772
Retriggerable One Pulse Mode (TIM15 Only)
773
UIF Bit Remapping
773
Figure 265. Retriggerable One Pulse Mode
773
Timer Input XOR Function (TIM15 Only)
775
Figure 266. Measuring Time Interval between Edges on 2 Signals
775
External Trigger Synchronization (TIM15 Only)
776
Figure 267. Control Circuit in Reset Mode
776
Figure 268. Control Circuit in Gated Mode
777
Slave Mode - Combined Reset + Trigger Mode
778
DMA Burst Mode
778
Figure 269. Control Circuit in Trigger Mode
778
Timer Synchronization (TIM15)
780
Using Timer Output as Trigger for Other Timers (TIM16/TIM17)
780
Debug Mode
780
TIM15 Registers
781
TIM15 Control Register 1 (TIM15_CR1)
781
TIM15 Control Register 2 (TIM15_CR2)
782
TIM15 Slave Mode Control Register (TIM15_SMCR)
784
TIM15 Dma/Interrupt Enable Register (TIM15_DIER)
785
Table 126. Timx Internal Trigger Connection
785
TIM15 Status Register (TIM15_SR)
786
TIM15 Event Generation Register (TIM15_EGR)
788
TIM15 Capture/Compare Mode Register 1 [Alternate]
789
(Tim15_Ccmr1)
789
(Tim15_Ccmr1)
790
TIM15 Capture/Compare Enable Register (TIM15_CCER)
793
Table 127. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
795
TIM15 Counter (TIM15_CNT)
796
TIM15 Prescaler (TIM15_PSC)
796
TIM15 Auto-Reload Register (TIM15_ARR)
796
TIM15 Repetition Counter Register (TIM15_RCR)
797
TIM15 Capture/Compare Register 1 (TIM15_CCR1)
797
TIM15 Capture/Compare Register 2 (TIM15_CCR2)
798
TIM15 Break and Dead-Time Register (TIM15_BDTR)
798
TIM15 DMA Control Register (TIM15_DCR)
801
TIM15 DMA Address for Full Transfer (TIM15_DMAR)
801
TIM15 Alternate Register 1 (TIM15_AF1)
802
TIM15 Input Selection Register (TIM15_TISEL)
803
TIM15 Register Map
804
Table 128. TIM15 Register Map and Reset Values
804
TIM16/TIM17 Registers
807
Timx Control Register 1 (Timx_Cr1)(X = 16 to 17)
807
Timx Control Register 2 (Timx_Cr2)(X = 16 to 17)
808
Timx Dma/Interrupt Enable Register (Timx_Dier)(X = 16 to 17)
809
Timx Status Register (Timx_Sr)(X = 16 to 17)
810
Timx Event Generation Register (Timx_Egr)(X = 16 to 17)
811
Timx Capture/Compare Mode Register 1 [Alternate] (Timx_Ccmr1)
812
Timx Capture/Compare Enable Register (Timx_Ccer)(X = 16 to 17)
815
Timx Counter (Timx_Cnt)(X = 16 to 17)
817
Table 129. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
817
Timx Prescaler (Timx_Psc)(X = 16 to 17)
818
Timx Auto-Reload Register (Timx_Arr)(X = 16 to 17)
818
Timx Repetition Counter Register (Timx_Rcr)(X = 16 to 17)
819
Timx Capture/Compare Register 1 (Timx_Ccr1)(X = 16 to 17)
819
Timx Break and Dead-Time Register (Timx_Bdtr)(X = 16 to 17)
820
Timx DMA Control Register (Timx_Dcr)(X = 16 to 17)
823
Timx DMA Address for Full Transfer (Timx_Dmar)(X = 16 to 17)
823
TIM16 Alternate Function Register 1 (TIM16_AF1)
824
TIM16 Input Selection Register (TIM16_TISEL)
825
TIM17 Alternate Function Register 1 (TIM17_AF1)
826
TIM17 Input Selection Register (TIM17_TISEL)
827
TIM16/TIM17 Register Map
829
Table 130. TIM16/TIM17 Register Map and Reset Values
829
Low-Power Timer (LPTIM)
831
Introduction
831
LPTIM Main Features
831
LPTIM Implementation
832
LPTIM Functional Description
832
LPTIM Block Diagram
832
Table 131. Stm32G0X1 LPTIM Features
832
Figure 270. Low-Power Timer Block Diagram (LPTIM1 and LPTIM2
832
LPTIM Pins and Internal Signals
833
LPTIM Input and Trigger Mapping
833
Table 132. LPTIM Input/Output Pins
833
Table 133. LPTIM Internal Signals
833
Table 134. LPTIM1 External Trigger Connection
833
Table 135. LPTIM2 External Trigger Connection
834
Table 136. LPTIM1 Input 1 Connection
834
Table 137. LPTIM1 Input 2 Connection
834
Table 138. LPTIM2 Input 1 Connection
834
LPTIM Reset and Clocks
835
Glitch Filter
835
Prescaler
836
Trigger Multiplexer
836
Table 139. Prescaler Division Ratios
836
Figure 271. Glitch Filter Timing Diagram
836
Operating Mode
837
Figure 272. LPTIM Output Waveform, Single Counting Mode Configuration
837
Figure 273. LPTIM Output Waveform, Single Counting Mode Configuration
838
Figure 274. LPTIM Output Waveform, Continuous Counting Mode Configuration
838
Timeout Function
839
Waveform Generation
839
Register Update
840
Figure 275. Waveform Generation
840
Counter Mode
841
Timer Enable
841
Timer Counter Reset
842
Encoder Mode
842
Table 140. Encoder Counting Scenarios
843
Debug Mode
844
LPTIM Low-Power Modes
844
Table 141. Effect of Low-Power Modes on the LPTIM
844
Figure 276. Encoder Mode Counting Sequence
844
LPTIM Interrupts
845
LPTIM Registers
845
Table 142. Interrupt Events
845
LPTIM Interrupt and Status Register (LPTIM_ISR)
846
LPTIM Interrupt Clear Register (LPTIM_ICR)
847
LPTIM Interrupt Enable Register (LPTIM_IER)
847
LPTIM Configuration Register (LPTIM_CFGR)
848
LPTIM Control Register (LPTIM_CR)
851
LPTIM Compare Register (LPTIM_CMP)
852
LPTIM Autoreload Register (LPTIM_ARR)
853
LPTIM Counter Register (LPTIM_CNT)
853
LPTIM Configuration Register 2 (LPTIM_CFGR2)
854
LPTIM Register Map
855
Table 143. LPTIM Register Map and Reset Values
855
Infrared Interface (IRTIM)
857
Figure 277. IRTIM Internal Hardware Connections
857
Independent Watchdog (IWDG)
858
Introduction
858
IWDG Main Features
858
IWDG Functional Description
858
IWDG Block Diagram
858
Figure 278. Independent Watchdog Block Diagram
858
Window Option
859
Hardware Watchdog
860
Register Access Protection
860
Debug Mode
860
IWDG Registers
861
IWDG Key Register (IWDG_KR)
861
IWDG Prescaler Register (IWDG_PR)
862
IWDG Reload Register (IWDG_RLR)
863
IWDG Status Register (IWDG_SR)
864
IWDG Window Register (IWDG_WINR)
865
IWDG Register Map
866
Table 144. IWDG Register Map and Reset Values
866
System Window Watchdog (WWDG)
867
Introduction
867
WWDG Main Features
867
WWDG Functional Description
867
WWDG Block Diagram
868
Enabling the Watchdog
868
Controlling the Down-Counter
868
How to Program the Watchdog Timeout
868
Figure 279. Watchdog Block Diagram
868
Figure 280. Window Watchdog Timing Diagram
869
Debug Mode
870
WWDG Interrupts
870
WWDG Registers
870
WWDG Control Register (WWDG_CR)
870
WWDG Configuration Register (WWDG_CFR)
871
WWDG Status Register (WWDG_SR)
872
WWDG Register Map
872
Table 145. WWDG Register Map and Reset Values
872
Real-Time Clock (RTC)
873
Introduction
873
RTC Main Features
873
RTC Functional Description
874
RTC Block Diagram
874
Figure 281. RTC Block Diagram
874
RTC Pins and Internal Signals
875
Table 146. RTC Input/Output Pins
875
Table 147. RTC Internal Input/Output Signals
875
Gpios Controlled by the RTC and TAMP
876
Table 148. RTC Interconnection
876
Table 149. PC13 Configuration
876
Clock and Prescalers
878
Table 150. RTC_OUT Mapping
878
Real-Time Clock and Calendar
879
Programmable Alarms
880
Periodic Auto-Wakeup
880
RTC Initialization and Configuration
881
Reading the Calendar
883
Resetting the RTC
884
RTC Synchronization
884
RTC Reference Clock Detection
885
RTC Smooth Digital Calibration
885
Timestamp Function
887
Calibration Clock Output
888
Tamper and Alarm Output
888
RTC Low-Power Modes
889
Table 151. Effect of Low-Power Modes on RTC
889
Table 152. RTC Pins Functionality over Modes
889
RTC Interrupts
890
RTC Registers
890
RTC Time Register (RTC_TR)
890
Table 153. Interrupt Requests
890
RTC Date Register (RTC_DR)
891
RTC Sub Second Register (RTC_SSR)
892
RTC Initialization Control and Status Register (RTC_ICSR)
892
RTC Prescaler Register (RTC_PRER)
894
RTC Wakeup Timer Register (RTC_WUTR)
895
RTC Control Register (RTC_CR)
895
RTC Write Protection Register (RTC_WPR)
898
RTC Calibration Register (RTC_CALR)
899
RTC Shift Control Register (RTC_SHIFTR)
900
RTC Timestamp Time Register (RTC_TSTR)
901
RTC Timestamp Date Register (RTC_TSDR)
901
RTC Timestamp Sub Second Register (RTC_TSSSR)
902
RTC Alarm a Register (RTC_ALRMAR)
903
RTC Alarm a Sub Second Register (RTC_ALRMASSR)
904
RTC Alarm B Register (RTC_ALRMBR)
905
RTC Alarm B Sub Second Register (RTC_ALRMBSSR)
906
RTC Status Register (RTC_SR)
906
RTC Masked Interrupt Status Register (RTC_MISR)
907
RTC Status Clear Register (RTC_SCR)
908
RTC Register Map
910
Table 154. RTC Register Map and Reset Values
910
Tamper and Backup Registers (TAMP)
912
Introduction
912
TAMP Main Features
912
TAMP Functional Description
913
TAMP Block Diagram
913
Figure 282. TAMP Block Diagram
913
TAMP Pins and Internal Signals
914
TAMP Register Write Protection
914
Table 155. TAMP Input/Output Pins
914
Table 156. TAMP Internal Input/Output Signals
914
Table 157. TAMP Interconnection
914
Tamper Detection
915
TAMP Low-Power Modes
917
TAMP Interrupts
917
TAMP Registers
917
Table 158. Effect of Low-Power Modes on TAMP
917
Table 159. Interrupt Requests
917
TAMP Control Register 1 (TAMP_CR1)
918
TAMP Control Register 2 (TAMP_CR2)
919
TAMP Filter Control Register (TAMP_FLTCR)
920
TAMP Interrupt Enable Register (TAMP_IER)
921
TAMP Status Register (TAMP_SR)
922
TAMP Masked Interrupt Status Register (TAMP_MISR)
923
TAMP Status Clear Register (TAMP_SCR)
924
TAMP Backup X Register (Tamp_Bkpxr)
925
TAMP Register Map
926
Table 160. TAMP Register Map and Reset Values
926
Inter-Integrated Circuit (I2C) Interface
927
Introduction
927
I2C Main Features
927
I2C Implementation
928
I2C Functional Description
928
Table 161. Stm32G0X1 I2C Implementation
928
I2C1 Block Diagram
929
Figure 283. I2C1 Block Diagram
929
I2C2 Block Diagram
930
Figure 284. I2C2 Block Diagram
930
I2C Pins and Internal Signals
931
I2C Clock Requirements
931
Mode Selection
931
Table 162. I2C Input/Output Pins
931
Table 163. I2C Internal Input/Output Signals
931
I2C Initialization
932
Figure 285. I2C Bus Protocol
932
Table 164. Comparison of Analog Vs. Digital Filters
933
Figure 286. Setup and Hold Timings
934
Table 165. I2C-Smbus Specification Data Setup and Hold Times
935
Software Reset
937
Figure 287. I2C Initialization Flowchart
937
Data Transfer
938
Figure 288. Data Reception
938
Figure 289. Data Transmission
939
I2C Slave Mode
940
Table 166. I2C Configuration
940
Figure 290. Slave Initialization Flowchart
942
Figure 291. Transfer Sequence Flowchart for I2C Slave Transmitter
944
Figure 292. Transfer Sequence Flowchart for I2C Slave Transmitter
945
Figure 293. Transfer Bus Diagrams for I2C Slave Transmitter
946
Figure 294. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=0
947
Figure 295. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=1
948
Figure 296. Transfer Bus Diagrams for I2C Slave Receiver
948
I2C Master Mode
949
Figure 297. Master Clock Generation
950
Table 167. I2C-Smbus Specification Clock Timings
951
Figure 298. Master Initialization Flowchart
952
Figure 299. 10-Bit Address Read Access with HEAD10R=0
952
Figure 300. 10-Bit Address Read Access with HEAD10R=1
953
Figure 301. Transfer Sequence Flowchart for I2C Master Transmitter for N≤255 Bytes
954
Figure 302. Transfer Sequence Flowchart for I2C Master Transmitter for N>255 Bytes
955
Figure 303. Transfer Bus Diagrams for I2C Master Transmitter
956
Figure 304. Transfer Sequence Flowchart for I2C Master Receiver for N≤255 Bytes
958
Figure 305. Transfer Sequence Flowchart for I2C Master Receiver for N >255 Bytes
959
Figure 306. Transfer Bus Diagrams for I2C Master Receiver
960
I2C_TIMINGR Register Configuration Examples
961
Table 168. Examples of Timing Settings for Fi2Cclk = 8 Mhz
961
Table 169. Examples of Timings Settings for Fi2Cclk = 16 Mhz
961
Smbus Specific Features
962
Table 170. Examples of Timings Settings for Fi2Cclk = 48 Mhz
962
Table 171. Smbus Timeout Specifications
964
Smbus Initialization
965
Figure 307. Timeout Intervals for T
965
Table 172. Smbus with PEC Configuration
966
Table 173. Examples of TIMEOUTA Settings for Various I2CCLK Frequencies
966
Smbus: I2C_TIMEOUTR Register Configuration Examples
967
Table 174. Examples of TIMEOUTB Settings for Various I2CCLK Frequencies
967
Smbus Slave Mode
968
Table 175. Examples of TIMEOUTA Settings for Various I2CCLK Frequencies (Max T IDLE = 50 Μs)
968
Figure 308. Transfer Sequence Flowchart for Smbus Slave Transmitter N Bytes + PEC
969
Figure 309. Transfer Bus Diagrams for Smbus Slave Transmitter (SBC=1)
969
Figure 310. Transfer Sequence Flowchart for Smbus Slave Receiver N Bytes + PEC
971
Figure 311. Bus Transfer Diagrams for Smbus Slave Receiver (SBC=1)
972
Figure 312. Bus Transfer Diagrams for Smbus Master Transmitter
973
Figure 313. Bus Transfer Diagrams for Smbus Master Receiver
975
Wakeup from Stop Mode on Address Match
976
Error Conditions
976
DMA Requests
978
Debug Mode
979
I2C Low-Power Modes
979
Table 176. Effect of Low-Power Modes on the I2C
979
I2C Interrupts
980
Table 177. I2C Interrupt Requests
980
I2C Registers
981
I2C Control Register 1 (I2C_CR1)
981
I2C Control Register 2 (I2C_CR2)
984
I2C Own Address 1 Register (I2C_OAR1)
987
I2C Own Address 2 Register (I2C_OAR2)
988
I2C Timing Register (I2C_TIMINGR)
989
I2C Timeout Register (I2C_TIMEOUTR)
990
I2C Interrupt and Status Register (I2C_ISR)
991
I2C Interrupt Clear Register (I2C_ICR)
993
I2C PEC Register (I2C_PECR)
994
I2C Receive Data Register (I2C_RXDR)
995
I2C Transmit Data Register (I2C_TXDR)
995
I2C Register Map
996
Table 178. I2C Register Map and Reset Values
996
Universal Synchonous Receiver Transmitter (USART)
998
USART Introduction
998
USART Main Features
999
USART Extended Features
1000
USART Implementation
1000
Table 179. Stm32G0X1 Features
1000
Table 180. USART / LPUART Features
1001
USART Functional Description
1002
USART Block Diagram
1002
Figure 314. USART Block Diagram
1002
USART Signals
1003
USART Character Description
1004
Figure 315. Word Length Programming
1005
USART Fifos and Thresholds
1006
USART Transmitter
1006
Figure 316. Configurable Stop Bits
1007
USART Receiver
1010
Figure 317. TC/TXE Behavior When Transmitting
1010
Figure 318. Start Bit Detection When Oversampling by 16 or 8
1011
Figure 319. Usart_Ker_Ck Clock Divider Block Diagram
1014
Figure 320. Data Sampling When Oversampling by 16
1015
Table 181. Noise Detection from Sampled Data
1016
Figure 321. Data Sampling When Oversampling by 8
1016
USART Baud Rate Generation
1017
Tolerance of the USART Receiver to Clock Deviation
1018
Table 182. Tolerance of the USART Receiver When BRR [3:0] = 0000
1019
USART Auto Baud Rate Detection
1020
Table 183. Tolerance of the USART Receiver When BRR[3:0] Is Different from 0000
1020
USART Multiprocessor Communication
1022
Figure 322. Mute Mode Using Idle Line Detection
1023
USART Modbus Communication
1024
Figure 323. Mute Mode Using Address Mark Detection
1024
USART Parity Control
1025
Table 184. USART Frame Formats
1025
USART LIN (Local Interconnection Network) Mode
1026
Figure 324. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
1027
USART Synchronous Mode
1028
Figure 325. Break Detection in LIN Mode Vs. Framing Error Detection
1028
Figure 326. USART Example of Synchronous Master Transmission
1029
Figure 327. USART Data Clock Timing Diagram in Synchronous Master Mode
1029
Figure 328. USART Data Clock Timing Diagram in Synchronous Master Mode
1030
Figure 329. USART Data Clock Timing Diagram in Synchronous Slave Mode
1031
USART Single-Wire Half-Duplex Communication
1032
USART Receiver Timeout
1032
USART Smartcard Mode
1033
Figure 330. ISO 7816-3 Asynchronous Protocol
1033
Figure 331. Parity Error Detection Using the 1.5 Stop Bits
1035
USART Irda SIR ENDEC Block
1037
Figure 332. Irda SIR ENDEC Block Diagram
1039
Figure 333. Irda Data Modulation (3/16) - Normal Mode
1039
Continuous Communication Using USART and DMA
1040
Figure 334. Transmission Using DMA
1041
RS232 Hardware Flow Control and RS485 Driver Enable
1042
Figure 335. Reception Using DMA
1042
Figure 336. Hardware Flow Control between 2 Usarts
1042
Figure 337. RS232 RTS Flow Control
1043
Figure 338. RS232 CTS Flow Control
1044
USART Low-Power Management
1045
Figure 339. Wakeup Event Verified (Wakeup Event = Address Match, FIFO Disabled)
1047
Figure 340. Wakeup Event Not Verified
1047
USART in Low-Power Modes
1048
Table 185. Effect of Low-Power Modes on the USART
1048
USART Interrupts
1049
Table 186. USART Interrupt Requests
1049
USART Registers
1050
USART Control Register 1 [Alternate] (USART_CR1)
1050
USART Control Register 1 [Alternate] (USART_CR1)
1054
USART Control Register 2 (USART_CR2)
1057
USART Control Register 3 (USART_CR3)
1061
USART Baud Rate Register (USART_BRR)
1066
USART Guard Time and Prescaler Register (USART_GTPR)
1066
USART Receiver Timeout Register (USART_RTOR)
1067
USART Request Register (USART_RQR)
1068
USART Interrupt and Status Register [Alternate] (USART_ISR)
1069
USART Interrupt and Status Register [Alternate] (USART_ISR)
1075
USART Interrupt Flag Clear Register (USART_ICR)
1080
USART Receive Data Register (USART_RDR)
1082
USART Transmit Data Register (USART_TDR)
1082
USART Prescaler Register (USART_PRESC)
1083
USART Register Map
1084
Table 187. USART Register Map and Reset Values
1084
Low-Power Universal Asynchronous Receiver
1086
Transmitter (LPUART)
1086
LPUART Introduction
1086
LPUART Main Features
1087
LPUART Implementation
1088
Table 188. Stm32G0X1 Features
1088
Table 189. USART / LPUART Features
1088
LPUART Functional Description
1089
LPUART Block Diagram
1089
Figure 341. LPUART Block Diagram
1089
LPUART Signals
1090
LPUART Character Description
1090
LPUART Fifos and Thresholds
1091
Figure 342. LPUART Word Length Programming
1091
LPUART Transmitter
1092
Figure 343. Configurable Stop Bits
1093
Figure 344. TC/TXE Behavior When Transmitting
1094
LPUART Receiver
1095
Figure 345. Lpuart_Ker_Ck Clock Divider Block Diagram
1098
LPUART Baud Rate Generation
1099
Table 190. Error Calculation for Programmed Baud Rates at Lpuart_Ker_Ck_Pres = 32,768 Khz
1099
Tolerance of the LPUART Receiver to Clock Deviation
1100
Table 191. Error Calculation for Programmed Baud Rates at Fck = 100 Mhz
1100
LPUART Multiprocessor Communication
1101
Table 192. Tolerance of the LPUART Receiver
1101
Figure 346. Mute Mode Using Idle Line Detection
1102
LPUART Parity Control
1103
Figure 347. Mute Mode Using Address Mark Detection
1103
LPUART Single-Wire Half-Duplex Communication
1104
Continuous Communication Using DMA and LPUART
1104
Figure 348. Transmission Using DMA
1105
Figure 349. Reception Using DMA
1106
RS232 Hardware Flow Control and RS485 Driver Enable
1107
Figure 350. Hardware Flow Control between 2 Lpuarts
1107
Figure 351. RS232 RTS Flow Control
1107
Figure 352. RS232 CTS Flow Control
1108
LPUART Low-Power Management
1109
Figure 353. Wakeup Event Verified
1111
Figure 354. Wakeup Event Not Verified
1111
LPUART in Low-Power Modes
1112
Table 194. Effect of Low-Power Modes on the LPUART
1112
LPUART Interrupts
1113
Table 195. LPUART Interrupt Requests
1113
LPUART Registers
1114
LPUART Control Register 1 [Alternate] (LPUART_CR1)
1114
LPUART Control Register 1 [Alternate] (LPUART_CR1)
1117
LPUART Control Register 2 (LPUART_CR2)
1120
LPUART Control Register 3 (LPUART_CR3)
1122
LPUART Baud Rate Register (LPUART_BRR)
1125
LPUART Request Register (LPUART_RQR)
1126
LPUART Interrupt and Status Register [Alternate] (LPUART_ISR)
1126
LPUART Interrupt and Status Register [Alternate] (LPUART_ISR)
1131
LPUART Interrupt Flag Clear Register (LPUART_ICR)
1134
LPUART Receive Data Register (LPUART_RDR)
1135
LPUART Transmit Data Register (LPUART_TDR)
1135
LPUART Prescaler Register (LPUART_PRESC)
1136
LPUART Register Map
1137
Table 196. LPUART Register Map and Reset Values
1137
Serial Peripheral Interface / Integrated Interchip Sound (SPI/I2S)
1139
Introduction
1139
SPI Main Features
1139
I2S Main Features
1140
SPI/I2S Implementation
1140
Table 197. Stm32G0X1 SPI and SPI/I2S Implementation
1140
SPI Functional Description
1141
General Description
1141
Figure 355. SPI Block Diagram
1141
Communications between One Master and One Slave
1142
Figure 356. Full-Duplex Single Master/ Single Slave Application
1142
Figure 357. Half-Duplex Single Master/ Single Slave Application
1143
Standard Multi-Slave Communication
1144
Figure 358. Simplex Single Master/Single Slave Application
1144
Multi-Master Communication
1145
Figure 359. Master and Three Independent Slaves
1145
Slave Select (NSS) Pin Management
1146
Figure 360. Multi-Master Application
1146
Communication Formats
1147
Figure 361. Hardware/Software Slave Select Management
1147
Figure 362. Data Clock Timing Diagram
1148
Configuration of SPI
1149
Figure 363. Data Alignment When Data Length Is Not Equal to 8-Bit or 16-Bit
1149
Procedure for Enabling SPI
1150
Data Transmission and Reception Procedures
1150
Figure 364. Packing Data in FIFO for Transmission and Reception
1153
Figure 365. Master Full-Duplex Communication
1156
Figure 366. Slave Full-Duplex Communication
1157
Figure 367. Master Full-Duplex Communication with CRC
1158
Figure 368. Master Full-Duplex Communication in Packed Mode
1159
SPI Status Flags
1160
SPI Error Flags
1161
NSS Pulse Mode
1162
TI Mode
1162
Figure 369. NSSP Pulse Generation in Motorola SPI Master Mode
1162
CRC Calculation
1163
Figure 370. TI Mode Transfer
1163
SPI Interrupts
1165
Table 198. SPI Interrupt Requests
1165
I2S Functional Description
1166
I2S General Description
1166
Figure 371. I2S Block Diagram
1166
Supported Audio Protocols
1167
Figure 372. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy)
1168
Figure 373. I 2 S Philips Standard Waveforms (24-Bit Frame)
1168
Figure 374. Transmitting 0X8Eaa33
1169
Figure 375. Receiving 0X8Eaa33
1169
Figure 376. I
1169
Figure 377. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
1169
Figure 378. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length
1170
Figure 379. MSB Justified 24-Bit Frame Length
1170
Figure 380. MSB Justified 16-Bit Extended to 32-Bit Packet Frame
1171
Figure 381. LSB Justified 16-Bit or 32-Bit Full-Accuracy
1171
Figure 382. LSB Justified 24-Bit Frame Length
1171
Figure 383. Operations Required to Transmit 0X3478Ae
1172
Figure 384. Operations Required to Receive 0X3478Ae
1172
Figure 385. LSB Justified 16-Bit Extended to 32-Bit Packet Frame
1172
Figure 386. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
1173
Figure 387. PCM Standard Waveforms (16-Bit)
1173
Start-Up Description
1174
Figure 388. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)
1174
Figure 389. Start Sequence in Master Mode
1175
Clock Generator
1176
Figure 390. Audio Sampling Frequency Definition
1176
Figure 391. I
1176
Table 199. Audio-Frequency Precision Using Standard 8 Mhz HSE
1178
I 2 S Master Mode
1179
I 2 S Slave Mode
1180
I2S Status Flags
1182
I2S Error Flags
1183
DMA Features
1184
I2S Interrupts
1184
Table 200. I2S Interrupt Requests
1184
SPI and I2S Registers
1185
SPI Control Register 1 (Spix_Cr1)
1185
SPI Control Register 2 (Spix_Cr2)
1187
SPI Status Register (Spix_Sr)
1189
SPI Data Register (Spix_Dr)
1190
SPI CRC Polynomial Register (Spix_Crcpr)
1191
SPI Rx CRC Register (Spix_Rxcrcr)
1191
SPI Tx CRC Register (Spix_Txcrcr)
1191
Spix_I2S Configuration Register (Spix_I2Scfgr)
1192
Spix_I2S Prescaler Register (Spix_I2Spr)
1194
SPI/I2S Register Map
1195
Table 201. SPI/I2S Register Map and Reset Values
1195
FD Controller Area Network (FDCAN)
1196
Introduction
1196
Table 202. CAN Subsystem I/O Signals
1196
Figure 392. CAN Subsystem
1197
FDCAN Main Features
1198
FDCAN Functional Description
1199
Figure 393. FDCAN Block Diagram
1199
Bit Timing
1200
Operating Modes
1201
Figure 394. Bit Timing
1201
Table 203. DLC Coding in FDCAN
1204
Figure 395. Transceiver Delay Measurement
1206
Figure 396. Pin Control in Bus Monitoring Mode
1207
Figure 397. Pin Control in Loop Back Mode
1209
Message RAM
1211
Figure 398. Message RAM Configuration
1211
Figure 399. Standard Message ID Filter Path
1214
Figure 400. Extended Message ID Filter Path
1215
Table 204. Possible Configurations for Frame Transmission
1217
FIFO Acknowledge Handling
1219
FDCAN Rx FIFO Element
1220
Table 205. Rx FIFO Element
1220
Table 206. Rx FIFO Element Description
1220
FDCAN Tx Buffer Element
1222
Table 207. Tx Buffer and FIFO Element
1222
Table 208. Tx Buffer Element Description
1222
FDCAN Tx Event FIFO Element
1224
Table 209. Tx Event FIFO Element
1224
Table 210. Tx Event FIFO Element Description
1224
FDCAN Standard Message ID Filter Element
1225
Table 211. Standard Message ID Filter Element
1225
Table 212. Standard Message ID Filter Element Field Description
1225
FDCAN Extended Message ID Filter Element
1226
Table 213. Extended Message ID Filter Element
1226
Table 214. Extended Message ID Filter Element Field Description
1226
FDCAN Registers
1227
FDCAN Core Release Register (FDCAN_CREL)
1227
FDCAN Endian Register (FDCAN_ENDN)
1227
FDCAN Data Bit Timing and Prescaler Register (FDCAN_DBTP)
1228
FDCAN Test Register (FDCAN_TEST)
1229
FDCAN RAM Watchdog Register (FDCAN_RWD)
1229
FDCAN CC Control Register (FDCAN_CCCR)
1230
FDCAN Nominal Bit Timing and Prescaler Register (FDCAN_NBTP)
1232
FDCAN Timestamp Counter Configuration Register (FDCAN_TSCC)
1233
FDCAN Timestamp Counter Value Register (FDCAN_TSCV)
1234
FDCAN Timeout Counter Configuration Register (FDCAN_TOCC)
1235
FDCAN Timeout Counter Value Register (FDCAN_TOCV)
1235
FDCAN Error Counter Register (FDCAN_ECR)
1236
FDCAN Protocol Status Register (FDCAN_PSR)
1236
FDCAN Transmitter Delay Compensation Register (FDCAN_TDCR)
1239
FDCAN Interrupt Register (FDCAN_IR)
1239
FDCAN Interrupt Enable Register (FDCAN_IE)
1242
FDCAN Interrupt Line Select Register (FDCAN_ILS)
1244
FDCAN Interrupt Line Enable Register (FDCAN_ILE)
1245
FDCAN Global Filter Configuration Register (FDCAN_RXGFC)
1245
FDCAN Extended ID and Mask Register (FDCAN_XIDAM)
1247
FDCAN High-Priority Message Status Register (FDCAN_HPMS)
1247
FDCAN Rx FIFO 0 Status Register (FDCAN_RXF0S)
1248
CAN Rx FIFO 0 Acknowledge Register (FDCAN_RXF0A)
1249
FDCAN Rx FIFO 1 Status Register (FDCAN_RXF1S)
1249
FDCAN Rx FIFO 1 Acknowledge Register (FDCAN_RXF1A)
1250
FDCAN Tx Buffer Configuration Register (FDCAN_TXBC)
1250
FDCAN Tx Fifo/Queue Status Register (FDCAN_TXFQS)
1251
FDCAN Tx Buffer Request Pending Register (FDCAN_TXBRP)
1252
FDCAN Tx Buffer Add Request Register (FDCAN_TXBAR)
1253
FDCAN Tx Buffer Cancellation Request Register (FDCAN_TXBCR)
1253
FDCAN Tx Buffer Transmission Occurred Register (FDCAN_TXBTO)
1254
FDCAN Tx Buffer Cancellation Finished Register (FDCAN_TXBCF)
1254
FDCAN Tx Buffer Transmission Interrupt Enable Register
1255
(Fdcan_Txbtie)
1255
FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
1255
(Fdcan_ Txbcie)
1255
FDCAN Tx Event FIFO Status Register (FDCAN_TXEFS)
1256
FDCAN Tx Event FIFO Acknowledge Register (FDCAN_TXEFA)
1256
FDCAN CFG Clock Divider Register (FDCAN_CKDIV)
1257
FDCAN Register Map
1258
Table 215. FDCAN Register Map and Reset Values
1258
Universal Serial Bus Full-Speed Host/Device Interface (USB)
1262
Introduction
1262
USB Main Features
1262
USB Implementation
1262
Table 216. Stm32G0X1 USB Implementation
1262
USB Functional Description
1263
Figure 401. USB Peripheral Block Diagram
1263
Description of USB Blocks Used in both Device and Host Modes
1265
Description of Host Frame Scheduler (HFS) Specific to Host Mode
1266
Programming Considerations for Device and Host Modes
1267
Generic USB Device Programming
1267
System and Power-On Reset
1267
Figure 402. Packet Buffer Areas with Examples of Buffer Description Table Locations
1269
Double-Buffered Endpoints and Usage in Device Mode
1274
Table 217. Double-Buffering Buffer Flag Definition
1275
Table 218. Bulk Double-Buffering Memory Buffers Usage (Device Mode)
1275
Double Buffered Channels: Usage in Host Mode
1276
Isochronous Transfers in Device Mode
1277
Table 219. Bulk Double-Buffering Memory Buffers Usage (Host Mode)
1277
Table 220. Isochronous Memory Buffers Usage
1278
Isochronous Transfers in Host Mode
1279
Suspend/Resume Events
1279
Table 221. Isochronous Memory Buffers Usage
1279
Table 222. Resume Event Detection
1281
Table 223. Resume Event Detection for Host
1282
USB and USB SRAM Registers
1283
Common Registers
1283
Table 224. Reception Status Encoding
1300
Table 225. Endpoint/Channel Type Encoding
1300
Table 226. Endpoint/Channel Kind Meaning
1300
Table 227. Transmission Status Encoding
1300
Buffer Descriptor Table
1302
Table 228. Definition of Allocated Buffer Memory
1303
USB Register Map
1306
Table 229. USB Register Map and Reset Values
1306
USB Type-C™ / USB Power Delivery Interface (UCPD)
1308
Introduction
1308
UCPD Main Features
1308
UCPD Implementation
1308
UCPD Functional Description
1309
Table 230. UCPD Implementation
1309
UCPD Block Diagram
1310
Table 231. UCPD Signals on Pins
1310
Figure 403. UCPD Block Diagram
1310
UCPD Reset and Clocks
1311
Table 232. UCPD Internal Signals
1311
Figure 404. Clock Division and Timing Elements
1311
Physical Layer Protocol
1312
Table 233. 4B5B Symbol Encoding Table
1312
Table 234. Ordered Sets
1314
Table 235. Validation of Ordered Sets
1314
Figure 405. K-Code Transmission
1314
Table 236. Data Size
1315
Figure 406. Transmit Order for Various Sizes of Data
1315
Figure 407. Packet Format
1316
Figure 408. Line Format of Hard Reset
1316
Figure 409. Line Format of Cable Reset
1317
Figure 410. bist Test Data Frame
1318
Figure 411. bist Carrier Mode 2 Frame
1318
UCPD BMC Transmitter
1319
Figure 412. UCPD BMC Transmitter Architecture
1319
UCPD BMC Receiver
1320
Figure 413. UCPD BMC Receiver Architecture
1320
UCPD Type-C Pull-Ups (Rp) and Pull-Downs (Rd)
1322
UCPD Type-C Voltage Monitoring and De-Bouncing
1322
UCPD Fast Role Swap (FRS) Signaling and Detection
1322
UCPD DMA Interface
1322
Wakeup from Stop Mode
1323
UCPD Programming Sequences
1323
Table 237. Coding for ANAMODE, ANASUBMODE and Link with Typec_Vstate_Ccx
1323
Table 238. Type-C Sequence (Source: 3A); Cable/Sink Connected (Rd on CC1; Ra on CC2)
1325
UCPD Low-Power Modes
1327
Table 239. Effect of Low Power Modes on the UCPD
1327
UCPD Interrupts
1328
Table 240. UCPD Interrupt Requests
1328
UCPD Registers
1329
UCPD Configuration Register 1 (UCPD_CFGR1)
1329
UCPD Configuration Register 2 (UCPD_CFGR2)
1331
UCPD Configuration Register 3 (UCPD_CFGR3)
1331
UCPD Control Register (UCPD_CR)
1332
UCPD Interrupt Mask Register (UCPD_IMR)
1335
UCPD Status Register (UCPD_SR)
1336
UCPD Interrupt Clear Register (UCPD_ICR)
1339
UCPD Tx Ordered Set Type Register (UCPD_TX_ORDSETR)
1340
UCPD Tx Payload Size Register (UCPD_TX_PAYSZR)
1341
UCPD Tx Data Register (UCPD_TXDR)
1341
UCPD Rx Ordered Set Register (UCPD_RX_ORDSETR)
1342
UCPD Rx Payload Size Register (UCPD_RX_PAYSZR)
1343
UCPD Receive Data Register (UCPD_RXDR)
1343
UCPD Rx Ordered Set Extension Register 1
1344
(Ucpd_Rx_Ordextr1)
1344
(Ucpd_Rx_Ordextr2)
1344
UCPD Register Map
1345
Table 241. UCPD Register Map and Reset Values
1345
HDMI-CEC Controller (CEC)
1347
Introduction
1347
HDMI-CEC Controller Main Features
1347
HDMI-CEC Functional Description
1348
HDMI-CEC Pin
1348
HDMI-CEC Block Diagram
1348
Message Description
1348
Table 242. HDMI Pin
1348
Figure 414. HDMI-CEC Block Diagram
1348
Bit Timing
1349
Figure 415. Message Structure
1349
Figure 416. Blocks
1349
Arbitration
1350
Figure 417. Bit Timings
1350
Figure 418. Signal Free Time
1350
SFT Option Bit
1351
Figure 419. Arbitration Phase
1351
Figure 420. SFT of Three Nominal Bit Periods
1351
Error Handling
1352
Bit Error
1352
Message Error
1352
Bit Rising Error (BRE)
1352
Figure 421. Error Bit Timing
1352
Short Bit Period Error (SBPE)
1353
Long Bit Period Error (LBPE)
1353
Figure 422. Error Handling
1353
Transmission Error Detection (TXERR)
1354
Table 243. Error Handling Timing Parameters
1354
Table 244. TXERR Timing Parameters
1355
Figure 423. TXERR Detection
1355
HDMI-CEC Interrupts
1356
Table 245. HDMI-CEC Interrupts
1356
HDMI-CEC Registers
1357
CEC Control Register (CEC_CR)
1357
CEC Configuration Register (CEC_CFGR)
1358
CEC Tx Data Register (CEC_TXDR)
1360
CEC Rx Data Register (CEC_RXDR)
1360
CEC Interrupt and Status Register (CEC_ISR)
1360
CEC Interrupt Enable Register (CEC_IER)
1362
HDMI-CEC Register Map
1364
Table 246. HDMI-CEC Register Map and Reset Values
1364
Debug Support (DBG)
1365
Overview
1365
Figure 424. Block Diagram of Stm32G0X1 MCU and Cortex
1365
Reference Arm Documentation
1366
Pinout and Debug Port Pins
1366
SWD Port Pins
1366
SW-DP Pin Assignment
1366
Table 247. SW Debug Port Pins
1366
Internal Pull-Up & Pull-Down on SWD Pins
1367
ID Codes and Locking Mechanism
1367
SWD Port
1367
SWD Protocol Introduction
1367
SWD Protocol Sequence
1367
SW-DP State Machine (Reset, Idle States, ID Code)
1368
Table 248. Packet Request (8-Bits)
1368
Table 249. ACK Response (3 Bits)
1368
Table 250. DATA Transfer (33 Bits)
1368
DP and AP Read/Write Accesses
1369
SW-DP Registers
1369
Table 251. SW-DP Registers
1369
SW-AP Registers
1370
Table 252. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
1370
Core Debug
1371
BPU (Break Point Unit)
1371
Table 253. Core Debug Registers
1371
BPU Functionality
1372
DWT (Data Watchpoint)
1372
DWT Functionality
1372
DWT Program Counter Sample Register
1372
MCU Debug Component (DBG)
1372
Debug Support for Low-Power Modes
1372
Debug Support for Timers, Watchdog and I 2 C
1373
DBG Registers
1373
DBG Device ID Code Register (DBG_IDCODE)
1373
Table 254. DEV_ID and REV_ID Field Values
1373
DBG Configuration Register (DBG_CR)
1374
DBG APB Freeze Register 1 (DBG_APB_FZ1)
1374
DBG APB Freeze Register 2 (DBG_APB_FZ2)
1376
DBG Register Map
1377
Table 255. DBG Register Map and Reset Values
1378
Device Electronic Signature
1379
Unique Device ID Register (96 Bits)
1379
Flash Memory Size Data Register
1380
Package Data Register
1380
Revision History
1382
Table 256. Document Revision History
1382
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