ST STM32G4 Series Reference Manual page 1029

RM0440
26.5.81 HRTIM fault input register 4 (HRTIM_FLTINR4)
Address offset: 0x40C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
FLT6 FLT6
FLT6CNT[3:0]
RSTM CRES
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 FLT6RSTM: Fault 6 reset mode
Refer to FLT5RSTM description.
Bit 14 FLT6CRES: Fault 6 counter reset
Refer to FLT5CRES description.
Bits 13:10 FLT6CNT[3:0]: Fault 6 counter
Refer to FLT5CNT description.
Bit 9 FLT6BLKS: Fault 6 blanking source
Refer to FLT5BLKS description.
Bit 8 FLT6BLKE: Fault 6 blanking enable
Refer to FLT6BLKE description.
Bit 7 FLT5RSTM: Fault 5 reset mode
This bit selects the FAULT5 counter reset mode
0: Fault 5 counter is reset on each reset / roll-over event
1: Fault 5 counter is reset on each reset / roll-over event only if no fault occurred during last counting
period.
This bitfield is written only when FLT5E enable bit is reset.
Bit 6 FLT5CRES: Fault 5 counter reset
This bit resets the FAULT5 counter. It is set by software and reset by hardware.
0: No action
1: Fault 5 counter is reset
28 27 26 25
Res. Res. Res.
12 11 10 9
FLT6
BLKS
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
FLT6 FLT5 FLT5
BLKE RSTM CRES
rw rw rw
RM0440 Rev 1
High-resolution timer (HRTIM)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
FLT5CNT[3:0]
rw rw rw rw
17 16
Res. Res.
1 0
FLT5 FLT5
BLKS BLKE
rw rw
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