ST STM32G4 Series Reference Manual page 1394

General-purpose timers (TIM15/TIM16/TIM17)
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 BKCMP4P: tim_brk_cmp4 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 12 BKCMP3P: tim_brk_cmp3 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 11 BKCMP2P: tim_brk_cmp2 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 10 BKCMP1P: tim_brk_cmp1 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 9 BKINP: TIMx_BKIN input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 8 Reserved, must be kept at reset value.
Bit 7 BKCMP7E: tim_brk_cmp7 enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
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This bit selects the tim_brk_cmp4 input sensitivity. It must be programmed together with the
BKP polarity bit.
0: tim_brk_cmp4 input is active high
1: tim_brk_cmp4 input is active low
in TIMx_BDTR register).
This bit selects the tim_brk_cmp3 input sensitivity. It must be programmed together with the
BKP polarity bit.
0: tim_brk_cmp3 input is active high
1: tim_brk_cmp3 input is active low
in TIMx_BDTR register).
This bit selects the tim_brk_cmp2 input sensitivity. It must be programmed together with the
BKP polarity bit.
0: tim_brk_cmp2 input is active high
1: tim_brk_cmp2 input is active low
in TIMx_BDTR register).
This bit selects the tim_brk_cmp1 input sensitivity. It must be programmed together with the
BKP polarity bit.
0: tim_brk_cmp1 input is active high
1: tim_brk_cmp1 input is active low
in TIMx_BDTR register).
This bit selects the TIMx_BKIN alternate function input sensitivity. It must be programmed
together with the BKP polarity bit.
0: TIMx_BKIN input is active high
1: TIMx_BKIN input is active low
in TIMx_BDTR register).
This bit enables the tim_brk_cmp7 for the timer's tim_brk input. tim_brk_cmp7 output is
'ORed' with the other tim_brk sources.
0: tim_brk_cmp7 input disabled
1: tim_brk_cmp7 input enabled
in TIMx_BDTR register).
RM0440 Rev 1
RM0440