ST STM32G4 Series Reference Manual page 1296

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Table 278. TIM2/TIM3/TIM4/TIM5 register map and reset values (continued)
Register
Offset
name
TIMx_CNT
0x024
Reset value 0
TIMx_PSC
0x028
Reset value
TIMx_ARR
0x02C
Reset value 1
0x030
TIMx_CCR1
0x034
Reset value 0
TIMx_CCR2
0x038
Reset value 0
TIMx_CCR3
0x03C
Reset value 0
TIMx_CCR4
0x040
Reset value 0
0x044..
Reserved
0x054
TIMx_ECR
0x058
Reset value
TIMx_TISEL
0x05C
Reset value
TIMx_AF1
0x060
Reset value
TIMx_AF2
0x064
Reset value
0x068..
Reserved
0x3D8
TIMx_DCR
0x3DC
Reset value
TIMx_DMAR
0x3E0
Reset value 0
1296/2083
CNT[30:16]
(CNT[31:16] on 32-bit timers only)
0 0 0 0 0 0 0 0 0
ARR[31:20]
(32-bit timers only)
1 1 1 1 1 1 1 1 1
CCR1[31:20]
(32-bit timers only)
0 0 0 0 0 0 0 0 0
CCR2[31:20]
(32-bit timers only)
0 0 0 0 0 0 0 0 0
CCR3[31:20]
(32-bit timers only)
0 0 0 0 0 0 0 0 0
CCR4[31:20]
(32-bit timers only)
0 0 0 0 0 0 0 0 0
PWPRSC
[2:0]
0 0 0 0 0
TI4SEL[3:0]
0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0
1 1 1 1 1 1 1 1
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Res.
PW[7:0]
0 0 0 0 0 0
TI3SEL[3:0]
0 0 0 0
ETRSEL
[3:0]
0 0 0 0
OCRSEL[
2:0]
0 0 0
Res.
DMAB[31:0]
0 0 0 0 0 0 0 0
RM0440 Rev 1
CNT[15:0]
0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0
ARR[19:0]
1 1 1 1 1 1 1 1
CCR1[19:0]
0 0 0 0 0 0 0 0
CCR2[19:0]
0 0 0 0 0 0 0 0
CCR3[19:0]
0 0 0 0 0 0 0 0
CCR4[19:0]
0 0 0 0 0 0 0 0
IPOS
[1:0]
0 0
TI2SEL[3:0]
0 0 0 0
DBL[4:0]
0 0 0 0 0
0 0 0 0 0 0 0 0
RM0440
0 0 0 0 0 0
0 0 0 0 0 0
1 1 1 1 1 1
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
IDIR
IE
[1:0]
0 0 0 0
TI1SEL[3:0]
0 0 0 0
DBA[4:0]
0 0 0 0 0
0 0 0 0 0 0