ST STM32G4 Series Reference Manual page 1386

General-purpose timers (TIM15/TIM16/TIM17)
29.8.9 TIMx counter (TIMx_CNT)(x = 16 to 17)
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
UIF
Res. Res. Res.
CPY
r
15 14 13
rw rw rw
Bit 31 UIFCPY: UIF Copy
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
29.8.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17)
Address offset: 0x28
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
1386/2083
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in
TIMx_CR1 is reset, bit 31 is reserved.
Non-dithering mode (DITHEN = 0)
The register holds the counter value.
Dithering mode (DITHEN = 1)
The register only holds the non-dithered part in CNT[15:0]. The fractional part is not
available.
12 11 10 9
rw rw rw rw
The counter clock frequency (tim_cnt_ck) is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in "reset mode").
24 23 22
Res. Res. Res.
8 7 6
CNT[15:0]
rw rw rw
8 7 6
PSC[15:0]
rw rw rw
RM0440 Rev 1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
5 4 3 2
rw rw rw rw
/ (PSC[15:0] + 1).
tim_psc_ck
RM0440
17 16
Res. Res.
1 0
rw rw
1 0
rw rw