ST STM32G4 Series Reference Manual page 1352

General-purpose timers (TIM15/TIM16/TIM17)
Bit 2 CC2IF: Capture/Compare 2 interrupt flag
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
Bit 0 UIF: Update interrupt flag
29.7.6 TIM15 event generation register (TIM15_EGR)
Address offset: 0x14
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIM15_SR register. Related interrupt or DMA transfer can occur if
1352/2083
refer to CC1IF description
If channel CC1 is configured as output: This flag is set by hardware when the counter
matches the compare value. It is cleared by software.
0: No match.
1: The content of the counter TIM15_CNT matches the content of the TIM15_CCR1 register.
When the contents of TIM15_CCR1 are greater than the contents of TIM15_ARR, the
CC1IF bit goes high on the counter overflow.
If channel CC1 is configured as input: This bit is set by hardware on a capture. It is
cleared by software or by reading the TIM15_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIM15_CCR1 register (An edge has been
detected on tim_ic1 which matches the selected polarity)
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow regarding the repetition counter value (update if repetition counter = 0) and if
the UDIS=0 in the TIM15_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIM15_EGR register, if URS=0
and UDIS=0 in the TIM15_CR1 register.
– When CNT is reinitialized by a trigger event (refer to
control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIM15_CR1 register.
12 11 10 9
Res. Res. Res.
DMA transfer can occur if enabled.
enabled
8 7 6
Res. BG TG COMG
w w
RM0440 Rev 1
Section 29.7.3: TIM15 slave mode
5 4 3 2
Res. Res. CC2G
rw w
RM0440
1 0
CC1G UG
w w