ST STM32G4 Series Reference Manual page 1276

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:12 IC4F[3:0]: Input capture 4 filter
Bits 11:10 IC4PSC[1:0]: Input capture 4 prescaler
Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bits 7:4 IC3F[3:0]: Input capture 3 filter
Bits 3:2 IC3PSC[1:0]: Input capture 3 prescaler
Bits 1:0 CC3S[1:0]: Capture/Compare 3 selection
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
28.5.10 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 2 to 5)
Address offset: 0x01C
Reset value: 0x0000 0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the
corresponding CCxS bits. All the other bits of this register have a different function for input
capture and for output compare modes. It is possible to combine both modes independently
(e.g. channel 1 in input capture mode and channel 2 in output compare mode).
31 30 29
Res. Res. Res. Res.
15 14 13
OC4CE OC4M[2:0]
rw rw rw
Output compare mode
Bits 31:25 Reserved, must be kept at reset value.
Bits 23:17 Reserved, must be kept at reset value.
Bit 15 OC4CE: Output compare 4 clear enable
1276/2083
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4
10: CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3
11: CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working
only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3
10: CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4
11: CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working
only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
28 27 26 25
Res. Res. Res.
12 11 10 9
OC4PE OC4FE CC4S[1:0]
rw rw rw rw
24 23 22
OC4M
Res. Res.
[3]
rw
8 7 6
OC3CE OC3M[2:0]
rw rw rw
RM0440 Rev 1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
OC3PE OC3FE
rw rw rw rw
RM0440
17 16
OC3M
Res.
[3]
rw
1 0
CC3S[1:0]
rw rw