ST STM32G4 Series Reference Manual page 1140

Advanced-control timers (TIM1/TIM8/TIM20)
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bit 4 CC4IE: Capture/compare 4 interrupt enable
0: CC4 interrupt disabled
1: CC4 interrupt enabled
Bit 3 CC3IE: Capture/compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled
Bit 2 CC2IE: Capture/compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
27.6.5 TIMx status register (TIMx_SR)(x = 1, 8, 20)
Address offset: 0x010
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. SBIF CC4OF CC3OF CC2OF CC1OF
rc_w0 rc_w0
1140/2083
28 27 26 25
Res. Res. Res.
12 11 10 9
rc_w0 rc_w0 rc_w0
24 23 22
Res. TERRF IERRF DIRF
rc_w0 rc_w0 rc_w0
8 7 6
B2IF BIF TIF COMIF
rc_w0 rc_w0 rc_w0 rc_w0
RM0440 Rev 1
21 20 19 18
IDXF Res. Res.
rc_w0
5 4 3 2
CC4IF CC3IF CC2IF
rc_w0 rc_w0 rc_w0
RM0440
17 16
CC6IF CC5IF
rc_w0 rc_w0
1 0
CC1IF UIF
rc_w0 rc_w0