ST STM32G4 Series Reference Manual page 1137

Advanced arm-based 32-bit mcus

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Advanced-control timers (TIM1/TIM8/TIM20)

Bits 6:4 TS[2:0]: Trigger selection

This bitfield is combined with TS[4:3] bits.

This bit-field selects the trigger input to be used to synchronize the counter.

00000: Internal Trigger 0 (tim_itr0)

00001: Internal Trigger 1 (tim_itr1)

00010: Internal Trigger 2 (tim_itr2)

00011: Internal Trigger 3 (tim_itr3)

00100: tim_ti1 Edge Detector (tim_ti1f_ed)

00101: Filtered Timer Input 1 (tim_ti1fp1)

00110: Filtered Timer Input 2 (tim_ti2fp2)

00111: External Trigger input (tim_etrf)

01000: Internal Trigger 0 (tim_itr4)

01001: Internal Trigger 1 (tim_itr5)

01010: Internal Trigger 1 (tim_itr6)

01011: Internal Trigger 1 (tim_itr7)

01100: Internal Trigger 1 (tim_itr8)

01101: Internal Trigger 1 (tim_itr9)

01110: Internal Trigger 1 (tim_itr10)

others: Reserved

Table 248: TIMx internal trigger connection on page 1153

for more details on tim_itrx

meaning for each Timer.

Note: These bits must be changed only when they are not used (e.g. when SMS=000) to

avoid wrong edge detections at the transition.

Bit 3 OCCS: OCREF clear selection

This bit is used to select the OCREF clear source.

0:tim_ocref_clr_int is connected to the tim_ocref_clr input

1: tim_ocref_clr_int is connected to tim_etrf

RM0440 Rev 1

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