ST STM32G4 Series Reference Manual page 1362

General-purpose timers (TIM15/TIM16/TIM17)
29.7.14 TIM15 capture/compare register 1 (TIM15_CCR1)
Address offset: 0x34
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:0 CCR1[19:0]: Capture/compare 1 value
1362/2083
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIM15_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIM15_CNT and signaled on tim_oc1 output.
Non-dithering mode (DITHEN = 0)
The register holds the compare value in CCR1[15:0]. The CCR1[19:16] bits are reset.
Dithering mode (DITHEN = 1)
The register holds the integer part in CCR1[19:4]. The CCR1[3:0] bitfield contains the
dithered part.
If channel CC1 is configured as input:
CR1 is the counter value transferred by the last input capture 1 event (tim_ic1). The
TIMx_CCR1 register is read-only and cannot be programmed.
Non-dithering mode (DITHEN = 0)
The register holds the capture value in CCR1[15:0]. The CCR1[19:16] bits are reset.
Dithering mode (DITHEN = 1)
The register holds the capture in CCR1[19:4]. The CCR1[3:0] bits are reset.
24 23 22
Res. Res. Res.
8 7 6
CCR1[15:0]
rw rw rw
RM0440 Rev 1
21 20 19 18
Res. Res. CCR1[19:16]
rw rw
5 4 3 2
rw rw rw rw
RM0440
17 16
rw rw
1 0
rw rw