ST STM32G4 Series Reference Manual page 1294

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
28.5.30 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5)
Address offset: 0x3E0
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
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Bits 31:0 DMAB[31:0]: DMA register for burst accesses
1294/2083
28 27 26 25
rw rw rw rw
12 11 10 9
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A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
24 23 22
DMAB[31:16]
rw rw rw
8 7 6
DMAB[15:0]
rw rw rw
RM0440 Rev 1
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0440
17 16
rw rw
1 0
rw rw