ST STM32G0B1VC Manuals
Manuals and User Guides for ST STM32G0B1VC. We have 1 ST STM32G0B1VC manual available for free PDF download: Reference Manual
ST STM32G0B1VC Reference Manual (1390 pages)
Brand: ST
|
Category: Microcontrollers
|
Size: 17 MB
Table of Contents
-
Glossary54
-
Introduction58
-
FLASH Registers100
-
Table 10108
-
Power Supplies119
-
(Bor)124
-
Low-Power Modes126
-
Run Mode131
-
Low-Power Modes132
-
Sleep Mode133
-
Stop 0 Mode135
-
Stop 1 Mode138
-
Standby Mode139
-
Shutdown Mode141
-
PWR Registers143
-
PWR Register Map158
-
Reset160
-
Power Reset160
-
System Reset160
-
RTC Domain Reset162
-
Clocks163
-
HSE Clock167
-
HSI16 Clock168
-
HSI48 Clock169
-
Pll169
-
LSE Clock170
-
LSI Clock170
-
ADC Clock172
-
RTC Clock172
-
Timer Clock173
-
Watchdog Clock173
-
Low-Power Modes177
-
RCC Registers178
-
(Rcc_Apbsmenr1)205
-
(Rcc_Apbsmenr2)208
-
(Rcc_Ccipr2)212
-
RCC Register Map217
-
Introduction221
-
CRS Interrupts225
-
CRS Registers226
-
CRS Register Map231
-
Introduction232
-
GPIO Registers241
-
(X =A to F)241
-
(X = a to F)242
-
(X = a to F)243
-
(X = a to F)244
-
(X = a to F)245
-
(X = a to F)246
-
SYSCFG Registers248
-
Introduction270
-
From ADC to TIM1272
-
And EXTI, to DAC273
-
TIM16, and TIM17273
-
And LPTIM2274
-
And COMP3274
-
TIM16, and TIM17275
-
And TIM17275
-
Introduction277
-
Dma278
-
DMA Transfers279
-
DMA Arbitration280
-
DMA Channels281
-
DMA Interrupts286
-
DMA Registers286
-
DMA Register Map295
-
Introduction298
-
DMAMUX Mapping299
-
DMAMUX Signals303
-
DMAMUX Channels303
-
DMAMUX Registers308
-
(Dmamux_Cxcr)308
-
(Dmamux_Csr)309
-
(Dmamux_Cfr)309
-
Main Features314
-
EXTI Mux321
-
EXTI Registers324
-
Introduction336
-
CRC Operation337
-
CRC Registers339
-
CRC Register Map342
-
Introduction343
-
ADC Connectivity352
-
Timings357
-
Data Management363
-
Oversampler373
-
Analog Watchdog375
-
Triggered Mode375
-
ADC Interrupts379
-
ADC Registers381
-
ADC Register Map402
-
Introduction404
-
DAC Data Format408
-
DAC Conversion410
-
DMA Requests411
-
Noise Generation411
-
Available)418
-
DAC Interrupts423
-
DAC Registers424
-
(Dac_Dhr12L1)428
-
(Dac_Dhr12L2)430
-
(Dac_Dhr12Ld)431
-
(Dac_Dhr8Rd)432
-
(Dac_Shsr1)437
-
(Dac_Shsr2)437
-
DAC Register Map440
-
Introduction442
-
Introduction445
-
Hysteresis449
-
COMP Interrupts451
-
COMP Registers451
-
Introduction459
-
RNG Operation464
-
RNG Clocking465
-
Error Management465
-
RNG Interrupts467
-
Introduction467
-
Data Collection468
-
RNG Registers469
-
RNG Register Map472
-
Introduction473
-
AES Interrupts509
-
AES Registers511
-
AES Register Map521
-
Time-Base Unit526
-
Counter Modes528
-
Clock Selection542
-
PWM Input Mode549
-
PWM Mode552
-
One-Pulse Mode570
-
DMA Burst Mode582
-
Debug Mode583
-
TIM1 Registers584
-
(Tim1_Ccmr1)595
-
(Tim1_Ccmr1)596
-
(Tim1_Ccmr2)599
-
(Tim1_Ccmr2)600
-
(Tim1_Ccer)602
-
(Tim1_Bdtr)608
-
(Tim1_Dmar)613
-
(Tim1_Ccmr3)614
-
Time-Base Unit627
-
Counter Modes629
-
Clock Selection639
-
PWM Input Mode646
-
PWM Mode648
-
One-Pulse Mode655
-
DMA Burst Mode668
-
Debug Mode669
-
Time-Base Unit703
-
Counting Mode705
-
Clock Source708
-
Debug Mode709
-
Time-Base Unit717
-
Counter Modes719
-
Clock Selection722
-
PWM Mode727
-
One-Pulse Mode728
-
Debug Mode729
-
TIM14 Registers730
-
Time-Base Unit745
-
Counter Modes747
-
Clock Selection752
-
PWM Mode760
-
One-Pulse Mode771
-
DMA Burst Mode778
-
Debug Mode780
-
TIM15 Registers781
-
(Tim15_Ccmr1)789
-
(Tim15_Ccmr1)790
-
Introduction831
-
Glitch Filter835
-
Prescaler836
-
Operating Mode837
-
Timeout Function839
-
Register Update840
-
Counter Mode841
-
Timer Enable841
-
Encoder Mode842
-
Debug Mode844
-
LPTIM Interrupts845
-
LPTIM Registers845
-
Introduction858
-
Window Option859
-
Debug Mode860
-
IWDG Registers861
-
Introduction867
-
Debug Mode870
-
WWDG Interrupts870
-
WWDG Registers870
-
Introduction873
-
RTC Interrupts890
-
RTC Registers890
-
RTC Register Map910
-
Introduction912
-
Tamper Detection915
-
TAMP Interrupts917
-
TAMP Registers917
-
Introduction927
-
Mode Selection931
-
Software Reset937
-
Data Transfer938
-
I2C Slave Mode940
-
I2C Master Mode949
-
Smbus Slave Mode968
-
Error Conditions976
-
DMA Requests978
-
Debug Mode979
-
I2C Interrupts980
-
I2C Registers981
-
I2C Register Map996
-
USART Implementation1000
-
USART Block Diagram1002
-
USART Signals1003
-
USART Transmitter1006
-
USART Receiver1010
-
USART Parity Control1025
-
USART Smartcard Mode1033
-
USART Interrupts1049
-
USART Registers1050
-
USART Register Map1084
-
Transmitter (LPUART)1086
-
LPUART Introduction1086
-
LPUART Main Features1087
-
LPUART Block Diagram1089
-
LPUART Signals1090
-
LPUART Transmitter1092
-
LPUART Receiver1095
-
LPUART Interrupts1113
-
LPUART Registers1114
-
LPUART Register Map1137
-
Introduction1139
-
SPI Main Features1139
-
I2S Main Features1140
-
General Description1141
-
Configuration of SPI1149
-
SPI Status Flags1160
-
SPI Error Flags1161
-
NSS Pulse Mode1162
-
TI Mode1162
-
CRC Calculation1163
-
SPI Interrupts1165
-
Figure 376. I1169
-
Start-Up Description1174
-
Clock Generator1176
-
Figure 391. I1176
-
I 2 S Master Mode1179
-
I 2 S Slave Mode1180
-
I2S Status Flags1182
-
I2S Error Flags1183
-
DMA Features1184
-
I2S Interrupts1184
-
SPI/I2S Register Map1195
-
Introduction1196
-
FDCAN Main Features1198
-
Bit Timing1200
-
Operating Modes1201
-
Message RAM1211
-
FDCAN Registers1227
-
(Fdcan_Txbtie)1255
-
(Fdcan_ Txbcie)1255
-
FDCAN Register Map1258
-
Introduction1262
-
USB Main Features1262
-
USB Implementation1262
-
Common Registers1283
-
USB Register Map1306
-
Introduction1308
-
UCPD Main Features1308
-
UCPD Implementation1308
-
UCPD Block Diagram1310
-
Table 236. Data Size1315
-
UCPD BMC Transmitter1319
-
UCPD BMC Receiver1320
-
UCPD DMA Interface1322
-
UCPD Low-Power Modes1327
-
UCPD Interrupts1328
-
UCPD Registers1329
-
(Ucpd_Rx_Ordextr1)1344
-
(Ucpd_Rx_Ordextr2)1344
-
UCPD Register Map1345
-
Introduction1347
-
HDMI-CEC Pin1348
-
Message Description1348
-
Table 242. HDMI Pin1348
-
Bit Timing1349
-
Figure 416. Blocks1349
-
Arbitration1350
-
SFT Option Bit1351
-
Error Handling1352
-
Bit Error1352
-
Message Error1352
-
HDMI-CEC Interrupts1356
-
HDMI-CEC Registers1357
-
Debug Support (DBG)1365
-
Overview1365
-
SWD Port Pins1366
-
SW-DP Pin Assignment1366
-
SWD Port1367
-
SW-DP Registers1369
-
SW-AP Registers1370
-
Core Debug1371
-
BPU Functionality1372
-
DWT Functionality1372
-
DBG Registers1373
-
DBG Register Map1377
-
Revision History1382
Advertisement
Advertisement