ST STM32G4 Series Reference Manual page 1014

High-resolution timer (HRTIM)
26.5.71 HRTIM fault input register 1 (HRTIM_FLTINR1)
Address offset: 0x3D0
Reset value: 0x0000 0000
31 30 29
FLT4LC
FLT4F[3:0]
K
rwo rw rw
15 14 13
FLT2LC
FLT2F[3:0]
K
rwo rw rw
Bit 31 FLT4LCK: Fault 4 lock
Refer to FLT5LCK description in HRTIM_FLTINR2 register.
Bits 30:27 FLT4F[3:0]: Fault 4 filter
Refer to FLT5F[3:0] description in HRTIM_FLTINR2 register.
Bit 26 FLT4SRC[0]: Fault 4 source bit 0
Refer to FLT5SRC[0] description in HRTIM_FLTINR2 register.
Bit 25 FLT4P: Fault 4 polarity
Refer to FLT5P description in HRTIM_FLTINR2 register.
Bit 24 FLT4E: Fault 4 enable
Refer to FLT5E description in HRTIM_FLTINR2 register.
Bit 23 FLT3LCK: Fault 3 lock
Refer to FLT5LCK description in HRTIM_FLTINR2 register.
Bits 22:19 FLT3F[3:0]: Fault 3 filter
Refer to FLT5F[3:0] description in HRTIM_FLTINR2 register.
Bit 18 FLT3SRC[0]: Fault 3 source bit 0
Refer to FLT5SRC[0] description in HRTIM_FLTINR2 register.
Bit 17 FLT3P: Fault 3 polarity
Refer to FLT5P description in HRTIM_FLTINR2 register.
Bit 16 FLT3E: Fault 3 enable
Refer to FLT5E description in HRTIM_FLTINR2 register.
Bit 15 FLT2LCK: Fault 2 lock
Refer to FLT5LCK description in HRTIM_FLTINR2 register.
Bits 14:11 FLT2F[3:0]: Fault 2 filter
Refer to FLT5F[3:0] description in HRTIM_FLTINR2 register.
Bit 10 FLT2SRC[0]: Fault 2 source bit 0
Refer to FLT5SRC[0] description in HRTIM_FLTINR2 register.
Bit 9 FLT2P: Fault 2 polarity
Refer to FLT2P description in HRTIM_FLTINR2 register.
Bit 8 FLT2E: Fault 2 enable
Refer to FLT5E description in HRTIM_FLTINR2 register.
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28 27 26 25
FLT4
FLT4P
SRC[0]
rw rw rw rw
12 11 10 9
FLT2
FLT2P
SRC[0]
rw rw rw rw
24 23 22
FLT3LC
FLT4E
K
rw rw rw
8 7 6
FLT1LC
FLT2E
K
rw rw rw
RM0440 Rev 1
21 20 19 18
FLT3
FLT3F[3:0]
SRC[0]
rw rw rw rw
5 4 3 2
FLT1
FLT1F[3:0]
SRC[0]
rw rw rw rw
RM0440
17 16
FLT3P FLT3E
rw rw
1 0
FLT1P FLT1E
rw rw