ST STM32G4 Series Reference Manual page 1210

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
28.4.8 PWM input mode
This mode allows to measure both the period and the duty cycle of a PWM signal connected
to single tim_tix input:
•
The TIMx_CCR1 register holds the period value (interval between two consecutive
rising edges)
•
The TIM_CCR2 register holds the pulse width (interval between two consecutive rising
and falling edges
This mode is a particular case of input capture mode. The set-up procedure is similar wit
hthe following differences:
•
Two ICx signals are mapped on the same tim_tix input.
•
These 2 ICx signals are active on edges with opposite polarity.
•
One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
The period and the pulse width of a PWM signal applied on tim_ti1 can be measured using
the following procedure:
1. Select the proper tim_tix_in[15..0] source (internal or external) with the TI1SEL[3:0] bits
in the TIMx_TISEL register.
2. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (tim_ti1 selected).
3. Select the active polarity for tim_ti1fp1 (used both for capture in TIMx_CCR1 and
counter clear): write the CC1P to '0' and the CC1NP bit to '0' (active on rising edge).
4. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (tim_ti1 selected).
5. Select the active polarity for tim_ti1fp2 (used for capture in TIMx_CCR2): write the
CC2P bit to '1' and the CC2NP bit to '0' (active on falling edge).
6. Select the valid trigger input: write the TS bits to 00101 in the TIMx_SMCR register
(tim_ti1fp1 selected).
7. Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
8. Enable the captures: write the CC1E and CC2E bits to '1 in the TIMx_CCER register.
1210/2083 RM0440 Rev 1
RM0440