ST STM32G4 Series Reference Manual page 1392

Advanced arm-based 32-bit mcus

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General-purpose timers (TIM15/TIM16/TIM17)

TIMx option register 1 (TIMx_OR1)(x = 16 to 17)

Address offset: 0x50

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 HSE32EN: HSE Divided by 32 enable

TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17)

Address offset: 0x054

Reset value: 0x0000 0000

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 DTPE: Deadtime preload enable

Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed

Bit 16 DTAE: Deadtime asymmetric enable

Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed

Bits 15:8 Reserved, must be kept at reset value.

This bit enables the HSE divider by 32 for the tim_ti1_in3. See

tim_ti1 input multiplexer

0: HSE divided by 32 disabled

1: HSE divided by 32 enabled

0: Deadtime value is not preloaded

1: Deadtime value preload is enabled

(LOCK bits in TIMx_BDTR register).

0: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register

1: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is

defined with DTGF[7:0] bits.

(LOCK bits in TIMx_BDTR register).

for details.

RM0440 Rev 1

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