ST STM32G4 Series Reference Manual page 1390

General-purpose timers (TIM15/TIM16/TIM17)
Bits 25:20 Reserved, must be kept at reset value.
Bits 19:16 BKF[3:0]: Break filter
This bit-field defines the frequency used to sample tim_brk input and the length of the digital
filter applied to tim_brk. The digital filter is made of an event counter in which N events are
needed to validate a transition on the output:
0000: No filter, tim_brk acts asynchronously
0001: f
0010: f
0011: f
0100: f
0101: f
0110: f
0111: f
1000: f
1001: f
1010: f
1011: f
1100: f
1101: f
1110: f
1111: f
This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the tim_brk input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0: tim_oc1 and tim_oc1n outputs are disabled or forced to idle state depending on the OSSI
1: tim_oc1 and tim_oc1n outputs are enabled if their respective enable bits are set (CC1E,
See tim_oc1/tim_oc1n enable description for more details
capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the tim_brk input
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 13 BKP: Break polarity
0: Break input tim_brk is active low
1: Break input tim_brk is active high
Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
Bit 12 BKE: Break enable
0: Break inputs (tim_brk and tim_sys_brk event) disabled
1; Break inputs (tim_brk and tim_sys_brk event) enabled
Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
1390/2083
=f
SAMPLING tim_ker_ck
=f
SAMPLING tim_ker_ck
=f
SAMPLING tim_ker_ck
=f /2, N=6
SAMPLING DTS
=f /2, N=8
SAMPLING DTS
=f /4, N=6
SAMPLING DTS
=f /4, N=8
SAMPLING DTS
=f /8, N=6
SAMPLING DTS
=f /8, N=8
SAMPLING DTS
=f /16, N=5
SAMPLING DTS
=f /16, N=6
SAMPLING DTS
=f /16, N=8
SAMPLING DTS
=f /32, N=5
SAMPLING DTS
=f /32, N=6
SAMPLING DTS
=f /32, N=8
SAMPLING DTS
bit.
CC1NE in TIMx_CCER register)
is not active)
in TIMx_BDTR register).
bits in TIMx_BDTR register).
2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
TIMx_BDTR register).
2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
, N=2
, N=4
, N=8
RM0440 Rev 1
(Section 29.8.8: TIMx
1383).
RM0440